Parthasarathi Dasgupta

A novel droplet routing algorithm for digital microfluidic biochips

One of the recent areas of research interest is the use of microfluidics for building up biochips, the digital microfluidic biochips (DMFB). This paper deals with a challenging problem related to the design of DMFB. Specifically the design problem considered is related to high performance droplet routing, where each droplet has single source location and single target location. The objectives are (i) minimizing the number of electrodes used in the DMFB, and (ii) minimizing the total routing time of all the droplets or arrival time of a droplet that is the last to arrive at its target(latest arrival time). We propose a simple algorithm for concurrent path allocation to multiple droplets, based on the Soukups routing algorithm [22], together with the use of stalling, and possible detouring of droplets in cases of contentions. Selection of the droplets is based on their respective source to target Manhattan paths. The empirical results are quite encouraging.

Searching networks with unrestricted edge costs

Best-first and depth-first heuristic search algorithms often assume underlying search graphs with only nonnegative edge costs and attempt to optimize simple objective functions. Applicability of these algorithms to graphs with both positive and negative edge costs is not completely studied. In the paper, two new problems are identified: one in computational geometry and the other in the layout design of very large scale integrated (VLSI) circuits. The former problem relates to a weight-balanced bipartitioning of a given set of points in a plane. The goal of the second problem is to find an area-balanced staircase path in a VLSI floorplan. Formulations of these problems lead to an interesting directed acyclic search graph with positive, zero and negative edge costs and an objective function of general nature. These problems are NP-hard. To solve such general problems optimally, search schemes are proposed. Experimental results reveal the efficacy and versatility of the proposed schemes, the depth-first scheme being the better choice. It is shown that the classical number-partitioning problem can also be formulated in this framework.

A heuristic method for constructing hexagonal Steiner minimal trees for routing in VLSI

In deep sub-micron regime, interconnect delays dominate VLSI circuit design. Thus, construction of cost-effective global routing trees is key to such designs. In order to reduce the interconnect delay, traditional Manhattan (M-) routing architectures are currently being replaced by the diagonal X architectures. A recent routing architecture is based on Y interconnects, involving the pervasive use of 0deg, 60deg, and 120deg oriented global and semi-global wirings. Unlike the X-routing, Y-routing Is observed to support regular routing grid, which as important for simplifying manufacturing processes and routing and design rule checking algorithms. In this paper, we propose a novel Y-routing algorithm which can solve reasonably sized problems in nominal time. The proposed method is capable of finding routing solutions for problem instances which could not be solved in reasonable time by some recently reported methods. Moreover, it can be easily extended for routing with any uniform orientation

Slicible Rectangular Graphs and Their Optimal Floorplans

Rectangular dualization method of floorplanning usually involves topology generation followed by sizing. Slicible topologies are often preferred for their simplicity and efficiency. While slicible topologies can be obtained efficiently, existing linear-time algorithms for topology generation from a given rectangular graph does not guarantee slicible topologies even if one exists. Moreover, the class of rectangular graphs, known as inherently nonslicible graphs, do not have any slicible topologies. In this article, new tighter sufficiency conditions for slicibility of rectangular graphs are postulated and utilized in the generation of area-optimal floorplans. These graph-theoretic conditions not only capture a larger class of slicible rectangular graphs but also help in reducing the total effort for topology generation, and in solving problems of larger size.

Minimizing Thermal Disparities during Placement in 3D ICs

During the Computer Aided Physical Design Cycle and specifically for high-performance VLSI circuits, on-chip power density plays a major role. The catalyst factors are increased scaling of technology, increasing number of components, higher frequency and bandwidth. The consumed power is usually converted into dissipated heat, affecting the performance and reliability of a chip. Moreover, recent trends in VLSI design entails the stacking of multiple active layers into a monolithic chip. These 3D chips have significantly larger power densities than their 2D counterparts. In this paper, we consider the placement of standard cells and gate arrays (modules) under thermal considerations. Our contribution includes a novel algorithm for placement of the gates or cells in the different active layers of a 3D IC such that: (i) the temperatures of the modules in each of the active layers is uniformly distributed, (ii) the maximum temperatures of each of the active layers is not too high, (iii) the maximum temperatures of the layers vary in a non-increasing manner from bottom layer to top layer to ensure an efficient heat dissipation of the whole chip. Experimental results on randomly generated and standard MCNC and ISPD benchmark instances are quite encouraging.

A unified approach to topology generation and optimal sizing of floorplans

Existing algorithms for floorplan topology generation by rectangular dualization usually do not consider sizing issues. In this paper, given a rectangularly dualizable adjacency graph and a set of aspect ratios of the modules, a topology which is likely to yield an optimally sized floorplan, is produced first in a top-down fashion by an AI-based search technique with novel heuristic estimates based on size parameters. It is shown that for any rectangular graph, there exists a feasible topology using only either straight or Z-cutlines recursively within a bounding rectangle. The significance of this result is four-fold: (1) considerable acceleration of the heuristic search, (2) topology generation with minimal number of nonslice cores, (3) guaranteed safe routing order without addition of pseudo modules, and (4) design of an efficient bottom-up heuristic for optimal sizing. Experimental results show that this integrated method elegantly solves floorplan optimization problem for general including inherently nonslicible adjacency graphs.

A Heuristic Method for Co-optimization of Pin Assignment and Droplet Routing in Digital Microfluidic Biochip

Design automation in Digital micro fluidic biochip is of immense importance in to days clinical diagnosis process. In this paper, we try to build a heuristic algorithm to simultaneously perform droplet routing and electrode actuation. The proposed method is capable of performing (i) droplet routing with minimal electrode usages in optimized routing completion time, and (ii) minimal number of control pin assignment on the routing path for successful droplet transportation. The proposed method is a co-optimization technique that finds the possible shortest path between the source and the target pair for a droplet and assigns control pins in an optimal manner to actuate the routing path. Intersection regions for multiple droplets are also assigned with pins in an efficient manner to avoid unnecessary mixing between several droplets. The proposed method is tested on various benchmarks and random test sets, and experimental results are quite encouraging.

Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations

In high-performance VLSI circuits, the on-chip power densities are playing dominant role due to increased scaling of technology, increasing number of components, frequency and bandwidth. The consumed power is usually converted into dissipated heat, affecting the performance and reliability of a chip. In this paper, we consider the placement of standard cells and gate arrays (modules) under thermal considerations. Our contributions include: (i) an algorithm for optimal placement of the gates or cells to minimize the possible occurrence of hot spots, (ii) results of sensitivity analysis of thermal characteristic of a layout with respect to the power densities of the modules in the layout, and identifying three classes of modules, and (iii) an algorithm for optimal placement of modules, with minimum possible occurrence of hot spots, and reasonable estimated interconnect lengths. Experimental results on randomly generated and standard benchmark instances are quite encouraging.

Revisiting VLSI interconnects in deep sub-micron: some open questions

Deep sub-micron technology has increased the design complexity of VLSI circuits. Design of routers now has to take care of the timing issues for faster design convergence. This has yielded wider scope of research in design and performance of interconnects. We focus on certain critical aspects of interconnects, and related open research issues. The discussions are on (i) the fidelity of delay estimators, and its use in finding global routing trees, (ii) a new class of routing trees, and (in) the evolution of new metric for interconnect performance measurement.

Monotone bipartitioning problem in a planar point set with applications to VLSI

A new problem called monotone bipartitioning of a planar point set is identified which is found to be useful in VLSI layout design. Let <i>F</i> denote a rectangular floor containing a set <i>A</i> of <i>n</i> points. The portion of a straight line formed by two points from the set <i>A</i> is called a line segment. A <i>monotone increasing path</i> (<i>MP</i>) in <i>F</i> is a connected and ordered sequence of line segments from the bottom-left corner of <i>F</i> to its top-right corner, such that the slope of each line segment is nonnegative, and each pair of consecutive line segments share a common point of <i>A</i>. An <i>MP</i> is said to be maximal (<i>MMP</i>) if no other point in <i>A</i> can be included in it preserving monotonicity. Let <i>A</i>^<i>L</i> denote the subset of <i>A</i> corresponding to the end points of the line segments in an <i>MMP</i>, <i>L</i>. The path <i>L</i> partitions the set of points <i>A</i>\<i>A</i>^<i>L</i> into two subsets lying on its two sides. The objective of monotone bipartitioning is to find an <i>MMP L</i>, such that the difference in the number of points in these two subsets is minimum. This problem can be formulated as finding a path between two designated vertices of an edge-weighted digraph (the weight of an edge being an integer lying in the range [-<i>n, n</i>]), for which the absolute value of the algebraic sum of weights is minimized. An <i>O</i>(<i>n</i>× <i>e</i>) time algorithm is proposed for this problem, where <i>e</i> denotes the number of edges of the graph determined from the geometry of the point set. The monotone bipartitioning problem has various applications to image processing, facility location, and plant layout problems. A related problem arises while partitioning a VLSI floorplan. Given a floorplan with <i>n</i> rectangular blocks, the goal is to find a monotone staircase channel from one corner of the floor to its diagonally opposite corner such that the difference in the numbers of blocks lying on its two sides is minimum. The problem is referred to as the staircase bipartitioning problem. The proposed algorithm for a point set can be directly used to solve this problem in <i>O</i>(<i>n</i>²) time. However, an improved <i>O</i>(<i>n</i>) time algorithm is reported for this special case. This leads to an <i>O</i>(<i>n</i> log <i>n</i>) time algorithm for hierarchical decomposition of a floorplan with a sequence of staircase channels. Staircase bipartitioning has many applications to channel and global routing.