Pascal Besson

Insights on fundamental mechanisms impacting Ge metal oxide semiconductor capacitors with high-k/metal gate stacks

Capacitance-voltage (CV) measurements on germanium metal oxide semiconductor (MOS) structures show unusual frequency behavior compared to their silicon counterparts—a low-frequency behavior of the high-frequency CV characteristics is observed in the inversion regime, and the experimental CV curves in the depletion regime exhibit large features that have been attributed to high densities of interface defects (Dit). In this paper, an electrical model is proposed to give insights on the fundamental mechanisms impacting Ge structures from a careful analysis of these CV measurements. Thanks to this analytical model, both CV and GV (conductance-voltage) characteristics have been accurately simulated over a large range of gate voltages and frequencies. The modeling of the strong inversion regime confirms that the generation-recombination of minority carriers is assisted by bulk traps and shows that a small level of impurities in Ge—in the 1015–1016percm3 range—can explain the frequency dispersion observed in the...

Measurement of Dipoles/Roll-Off /Work Functions by Coupling CV and IPE and Study of Their Dependence on Fabrication Process

We study the effective metal gate work function (WFMeff) of different metal/high-κ gate stacks. Both capacitance versus voltage measurement and internal photo emission measurement were used, leading to a better understanding of the WFMeff variations. We demonstrate that these variations are related to two main process dependent parameters, a voltage drop at the high- κ/SiO2 interface and the metal work function. These two parameters are studied for various process conditions.

Impact of crystallinity of High-k oxides on Vt instabilities of NMOS devices assessed by physical and electrical measurements

This paper investigates the impact of crystallinity of HfO2 oxides on VT instabilities. Wet etch rate measurements enhances a critical thickness tHK C for HfO2 which marks the transition between a monoclinic crystalline phase to a near amorphous state, both clearly identified by ATR FTIR. Using electrical measurements and modeling, it is demonstrated that this transition from the crystalline phase to an amorphous state is accompanied by a strong reduction of the density of bulk HfO2 defects responsible for electron trapping, Prevents the crystallization of an high-k layer is therefore fundamental to improve its BTI reliability.

Critical Thickness Threshold in HfO2 Layers

Wet etch ability of HfO2 high k layers in diluted HF solutions is very attractive to achieve an efficient selective removal with respect to silicon consumption and metal gate compatibility for advanced technology node. Unfortunately in most cases HfO2 layers can not be etched in a wet mixture after the gate stack formation and dry etch. This behavior is now clearly correlated to the monoclinic crystalline phase [1;2]. This phase can be either an “as deposited” state in the case of high temperature deposition mode such as MOCVD, or a post integration state related to added thermal budget as for ALCVD. In this study, the HfO2 etch rate with a diluted HF/HCl chemical solution was tightly monitored as a function of both ALCVD and MOCVD deposition modes, under different annealing conditions and different deposited thicknesses.

Wet Etching Step Evolutions for Selective Removal on Silicide or Germanide Applications

Initially, silicides were firstly used in LSI devices as polycides (MoSi2, WSi2) in contact to poly Si gate electrodes [1]. The polycide/poly Si gate was directly patterned from a sputtered polycide/poly Si stack layer according to a quite simple integration scheme. However, due to the increase of the resistances of source, drain and gate with the reduction of device dimensions, the introduction of a low resistive silicide layer not only on top gate but also on source and drain has became mandatory. Consequently, salicide (self-aligned silicide) technology was introduced in the early 1990s.

Gate-last integration on planar FDSOI MOSFET: Impact of mechanical boosters and channel orientations

We present for the first time Gate-Last (GL) planar Fully Depleted (FD) SOI MOSFETs featuring both ultra thin silicon body (3-5 nm) and BOX (25 nm). Transistors with metal-last on high-k first (TiN/HfSiON) have been successfully fabricated down to 15nm gate length. We have thoroughly characterized the gate stack (reliability, work-function tuning on Equivalent Oxide Thickness EOT=0.85nm) and transport (hole mobility, Raccess) for different surface and channel orientations. We report excellent ION, p=1020μA/μm at IOFF, p=100nA/μm at VDD=0.9V supply voltage for <;110> pMOS channel on (001) surface with in-situ boron doped SiGe Raised Source and Drain (RSD) and compressive CESL. This is explained by the high efficiency of the strain transfer into the ultra-thin channel, as evidenced by physical strain measurements (dark field holography).

Germanium Surface Passivation Using Ozone Gaseous Phase

Introduction As silicon tends towards ultimate physical limitations for high-performance devices, germanium is extensively investigated for its high electron and hole mobility advantages [1]. As for silicon, advanced integration node implies the use of very efficient germanium cleaning sequences to gain yield. However, germanium surface sensitivity against most of the conventional wet solutions is a major issue [2]. Specific wet chemical processes also need to be developed to clean and prepare germanium surfaces before being integrated. In this study, the influence of various chemical treatments on germanium surfaces state is investigated using AR-XPS analysis. Then, a new method to efficiently passivate a germanium surface is described. Using gaseous ozone phase on a spin-on single wafer cleaning tool, we effectively managed to grow a GeO2 layer which is, according to AR-XPS analysis, stable in time.

Barrier and Copper Seedlayer Wet Etching

This paper summarizes the process development of TiN barrier etching in presence of copper, for a thick copper level in BICMOS technology. In an industrial context, we have chosen to use a SC1 chemistry in a spin etch single wafer tool. The SC1 composition and therefore the pH level allows - the barrier to be etched with no metallic residues, ( if not clear this can be a source for shorts) - control of the selectivity between copper and TiN - control of lateral etching under copper lines, the possible source of open chains by W attack during TiN etch. The electrical results show a robust process according to current specifications, in terms of leakage and via resistance with a fresh chemistry approach. In fact, the recirculation of SC1 is not possible due to substantial concentration changes during processing, high evaporation rate of Ammonia and high decomposition rate of Peroxide in the presence of copper on surface wafer.

Reduction of defect density on blanks: application to the extreme ultraviolet lithography

Abstract Our laboratory is involved in the French EUV (Extreme Ultra-Violet) program PREUVE to develop Mo/Si mirrors for blanks free of defects by using an ion beam sputtering deposition technique. This paper illustrates a reduction strategy used to lead to an EUV mirror with a defect density as low as possible. One of the methods adopted is the analysis of the process step by step, therefore, the defect number added by each process step has been quantified. It appears that the most critical step is substrate cleanness. Today, our best performance for a final mirror is 1.2 def/cm 2 with a defect size >200 nm. This value has been measured on our home-made counting device COMNET. Our counting device has been validated by comparison with a commercial tool. Two improvements have been implemented on COMNET to increase its routine performance which allows to detect particles of 200 nm. The first one is the sample illumination with a laser in oblique incidence (60°) which increases the signal-to-noise ratio. The noise is the roughness of the sample. The second one is the implementation of a cooled CCD camera with a variable exposure time. Thanks to these improvements, the detection of particles with a diameter size of 155 nm has been demonstrated. On the basis of the experimental results and calculations, the detection of 100 nm particles on silicon and EUV blanks can be reasonably predicted.

Cross-Contamination Risk Evaluation during Fabrication of III-V Devices in a Silicon Processing Environment

III-V semiconductor compounds are increasingly studied for their interesting properties in the fields of microelectronics, optoelectronics, infrared detectors or solar cells. Firstly, they are promising candidates to replace silicon as a channel material. As CMOS scales beyond the 22 nm node it is widely expected that new higher mobility channel materials such as InxGa1-xAs will have to be introduced [1]. On the other hand, III-V materials have a direct bandgap making them useful for optoelectronic devices or high-efficiency multijunction photovoltaic cells. For these applications InP, GaAs and their alloys as InxGa1-xAs and GaxIn1-xP are investigated [2]. Depending on the targeted applications, several possible integration routes of III-V components could be considered: from 100 mm III-V substrates to III-V epitaxial layers grown on 300 mm silicon wafers as well as a few square centimetres chips bonded on 200 or 300 mm carrier wafers for photonics applications. In all cases, the manufacturing of devices requires a multitude of wet chemical steps including selective etching steps (from a few nanometres up to several microns) and cleaning steps (metallic or particles contamination removal).