Pascale Francis

A comprehensive compact-modeling methodology for spiral inductors in silicon-based RFICs

A new comprehensive wide-band compact-modeling methodology for on-chip spiral inductors is presented. The new modeling methodology creates an equivalent-circuit model consisting of frequency-independent circuit elements. A fast automated extraction procedure is developed for determining the circuit element values from two-port S-parameter measurement data. The methodology is extremely flexible in allowing for accurate modeling of general classes of spiral inductors on high- or low-resistivity substrate and for large spirals exhibiting distributed trends. The new modeling methodology is applied to general classes of spirals with various sizes and substrate parameters. The extracted models show excellent agreement with the measured data sets over the frequency range of 0.1-10 GHz.

Precision electrical trimming of very low TCR poly-SiGe resistors

Precision electrical trimming of stacked Si/SiGe polycrystalline resistors available from the extrinsic base structure of a SiGe BiCMOS technology has been demonstrated for the first time. It is shown that pulse current trimming techniques can be used to trim the poly-SiGe resistors by up to 50% from their original values with accuracy better than /spl plusmn/0.5%. The temperature coefficient of resistance (TCR) is shown to be linearly proportional to the percent change in electrically trimmed poly-SiGe resistance. Finally, we demonstrate resistance cycling using an electrical trim/recovery sequence, indicating that the technique is reversible and is governed by dopant segregation/diffusion mechanisms. The results are consistent with those obtained on conventional polysilicon resistors suggesting that the introduction of a strained SiGe layer does not adversely affect the electrical trim properties of these resistors.

A new wideband compact model for spiral inductors in RFICs

A new wide-band compact model for planar spiral inductors on lossy silicon substrate is presented. Transformer loops are used in the series branch of the equivalent circuit model to include the effects of the frequency-dependent losses, in particular eddy-current loss in the silicon substrate. The new compact model and the standard 9-element model are extracted from measurement data of a typical 1.5-nH spiral fabricated on a low-resistivity CMOS substrate over a frequency range of 0.1 to 10 GHz. The frequency-dependent series resistance and inductance as well as the quality factor obtained with the new model are in excellent agreement with the measured results.

A new compact model for monolithic transformers in silicon-based RFICs

A new compact model for monolithic transformers on silicon substrates is presented. The new lumped-element equivalent circuit model employs transformer loops to represent skin and proximity effects including eddy current loss in the windings of the transformer. In addition to the self-resistances and self-inductances of the windings, the effects of the frequency-dependent mutual resistance and mutual inductance are included in the model. The new compact model has been applied to a stacked transformer on a 10-/spl Omega//spl middot/cm CMOS substrate. The extracted circuit model shows very good agreement with data obtained by full-wave electromagnetic simulation and measurement over the frequency range of 0.1-10GHz.

Surface-states effects on GaAs FET electrical performance

We analyzed the effects of surface-states on GaAs FET electrical performance with a two-dimensional (2-D) device simulator that used a surface-state model based on Shockley-Read-Hall (SRH) statistics. We found that under typical FET operating conditions, electron-trap-type surface-states pin the surface potential to the electron quasi-Fermi level (that is, the n-type channel potential), whereas hole-trap-type surface-states pin it to the hole quasi-Fermi level (that is, the gate potential). This difference affects both the electric-field distribution along the channel and the drain current values. The transient responses to step-bias application at the gate and at the drain showed slow transients due to the surface-states, but the directions of the shifts were opposite for the different trap-types. We explain these phenomena using a theory based on Shockley-Read-Hall statistics for the surface-states.

Wide-band compact modeling of spiral inductors in RFICs

A new wide-band compact modeling methodology for planar spiral inductors on lossy silicon substrate is presented. The new ideal lumped-element equivalent circuit model employs transformer loops in the series branch to include the effects of the frequency-dependent losses, in particular eddy-current loss in the bulk silicon substrate. A robust automated extraction procedure is employed to extract the element values of the new compact model. The new automated modeling methodology has been applied to a typical 1.5 nH spiral fabricated on a low-resistivity CMOS substrate. The frequency-dependent series resistance and inductance as well as the quality factor obtained with the new wideband model are in excellent agreement with the measured results over a 10 GHz bandwidth.

Physics, Technology, and Modeling of Complementary Asymmetric MOSFETs

The physics, technology, and modeling of complementary asymmetric MOSFETs are reviewed and illustrated with statistically representative silicon data from a recent manufacturing implementation, in which the transistors for the secondary power supply voltage are offered in asymmetric and symmetric constructions. The in-depth analysis of the device physics of asymmetric transistors provides new insights into their physical operation and into the operation of transistors using halo implants in general. The variability, matching, and noise implications of using halo implants are also analyzed, concluding that both asymmetric and symmetric devices need to be offered for uncompromised circuit design. The challenges associated with the compact modeling the asymmetric transistors are also reviewed and illustrated. The preferred manufacturing implementation uses retrograde wells with no dopant fillers at the surface, while avoiding the drain-to-source punch-through by source-side-only halo implants. In addition to the known switching speed and maximum voltage gain advantages of the asymmetric transistors, this particular device architecture offers superior hot-carrier reliability and transistor design flexibility. The availability of retrograde wells enables construction of high-reliability complementary extended-drain MOSFETs for a third higher power supply voltage.

Wide-band distributed modeling of spiral inductors in RFICs

A new wide-band model for planar spiral inductors on silicon substrate consisting of ideal lumped elements is presented. The equivalent circuit model captures the distributed behavior of the spiral for electrically large devices in particular with low self-resonant frequency. A fast, automated extraction procedure is developed for determining the circuit element values from two-port S-parameter data. The new modeling methodology is applied to extract a distributed model from the measured S-parameters of an electrically large 1.5-nH spiral. The extracted model shows excellent agreement with the measured data over a frequency range of 0.1 to 10 GHz.

Compact modeling of differential spiral inductors in Si-based RFICs

A new modeling methodology for on-chip differential spiral inductors is presented. The presented model consists entirely of frequency-independent circuit elements. An automated extraction technique is presented for determining the circuit elements from two two-port S-parameter measurement data sets. The new method allows for a single model to accurately capture the single-ended and differential operations of the device. The modeling methodology is applied to a sample differential spiral inductor. The extracted model shows excellent accuracy in comparison with device measurements over the frequency range 0.2 to 10.2 GHz.

Scalable Spice Modeling of Integrated Power LDMOS Device Using a Cell-Based Building Block Approach

This paper illustrates a scalable Spice modeling method for an integrated power LDMOS device based on a multi-cell array structure. Depending on the location in the array (corner, edge, inner), three different types of cells were identified to have distinct electrical characteristics. Each cell type was modeled independently and was treated as a building block for the final scalable model. The three building block models could be relatively accurately generated because they were required to fit only one cell with fixed channel length and width. By combining the three building blocks, a scalable Spice model was created.