Vladislav Vashchenko

High holding voltage cascoded LVTSCR structures for 5.5-V tolerant ESD protection clamps

This paper presents a new design concept for the control of the holding voltage of LVTSCR ESD protection structures by realizing a negative feedback in the p emitter. The negative feedback is implemented by the creation of a voltage drop using embedded circuit elements. The final clamp voltage is tuned to exceed the power supply level, thus eliminating the potential for latchup. The design is validated by ESD pulse measurements performed on test structures with cascoded, triggered LVTSCRs for 5.5-V tolerant I/O pins in an 0.18-/spl mu/m CMOS process. The results of the first part of the study were used to propose another design for the LVTSCR with a high holding voltage based on emitter area reduction. The proposed device is validated using three-dimensional simulations and experimental analysis.

Accelerated aging system for prognostics of power semiconductor devices

Prognostics is an engineering discipline that focuses on estimation of the health state of a component and the prediction of its remaining useful life (RUL) before failure. Health state estimation is based on actual conditions and it is fundamental for the prediction of RUL under anticipated future usage. Failure of electronic devices is of great concern as future aircraft will see an increase of electronics to drive and control safety-critical equipment throughout the aircraft. Therefore, development of prognostics solutions for electronics is of key importance. This paper presents an accelerated aging system for gate-controlled power transistors. This system allows for the understanding of the effects of failure mechanisms, and the identification of leading indicators of failure which are essential in the development of physics-based degradation models and RUL prediction. In particular, this system isolates electrical overstress from thermal overstress. Also, this system allows for a precise control of internal temperatures, enabling the exploration of intrinsic failure mechanisms not related to the device packaging. By controlling the temperature within safe operation levels of the device, accelerated aging is induced by electrical overstress only, avoiding the generation of thermal cycles. The temperature is controlled by active thermal-electric units. Several electrical and thermal signals are measured in-situ and recorded for further analysis in the identification of leading indicators of failures. This system, therefore, provides a unique capability in the exploration of different failure mechanisms and the identification of precursors of failure that can be used to provide a health management solution for electronic devices.

Comparison of ESD protection capability of lateral BJT, SCR and bidirectional. SCR for hi-voltage BiCMOS circuits

Triggering structures BJT, SCR and bi-directional SCR for high voltage BiCMOS process onchip ESD protection have been developed and analyzed using physical process and device simulation and pulse measurements. A ten-fold increase in the protection levels compared to the reference BJT structures have been demonstrated using a cylindrical lateral SCR and bidirectional SCR.

Prognostics of power MOSFET

This paper demonstrates how to apply prognostics to power MOSFETs (metal oxide field effect transistor). The methodology uses thermal cycling to age devices and Gaussian process regression to perform prognostics. The approach is validated with experiments on 100V power MOSFETs. The failure mechanism for the stress conditions is determined to be die-attachment degradation. Change in ON-state resistance is used as a precursor of failure due to its dependence on junction temperature. The experimental data is augmented with a finite element analysis simulation that is based on a two-transistor model. The simulation assists in the interpretation of the degradation phenomena and SOA (safe operation area) change.

Physical limitation of the cascoded snapback NMOS ESD protection capability due to the non-uniform turn-off

The nonlinear effects and physical failure mechanism in over-voltage protection NMOS snapback structures during ESD operation have been analyzed with the use of experimental test structures as well as process and device simulations. A phenomenological explanation has been provided to account for the effect due to substrate type and the use of a so-called ESD implant. A generic design solution for the cascoded snapback NMOS structure suitable for 5-V tolerant I/O applications is proposed, one that delivers robust operation and eliminates the requirement for an additional ESD implant.

Active Control of the Triggering Characteristics of NPN BJT, BSCR and NLDMOS-SCR Devices

This study presents a new solution for ESD protection of high-voltage and high-speed pins in power analog circuits, such as voltage switching regulators. A mixed device-circuit ESD solution is validated experimentally using transmission line pulse measurements. It is demonstrated that the triggering characteristics of both bipolar and MOS ESD devices can be successfully controlled as a function of operation mode in a large voltage range using an active circuit and control electrodes. An example of an active circuit to control the triggering characteristics of the ESD devices is presented. A practical implementation is verified for 50 V NPN BJT, Bipolar SCR and LDMOS-SCR snapback ESD devices. The advantage of the proposed solution over snapback ESD devices triggered by avalanche or displacement current is discussed for high-speed power analog applications.

Implementation of dual-direction SCR devices in analog CMOS process

Implementation of the dual-direction SCRs in a 5 V analog CMOS process was studied using pulsed I-V measurements and numerical simulations. A positive feedback mechanism associated with a parasitic vertical PNP was found, discussed and further utilized to improve the SCR latch-up robustness. The 2kV HBM 200V MM ESD protection capabilities with the holding voltage exceeding 5V were demonstrated in the ESD cells with the footprint size smaller than 2100 sq. um.

Turn-On Voltage Control in BSCR and LDMOS-SCR by the Local Blocking Junction Connection

The problem of local ESD protection of power arrays is addressed at the device level. A wide voltage range of the pulsed dV/dt turn-on is achieved using a local blocking junction connection. The approach is experimentally validated on both examples of bipolar SCR and NLDMOS-SCR devices and implemented in a 0.5mum 24V BiCMOS process

ESD protection window targeting using LDMOS-SCR devices with PWELL-NWELL super-junction

A variety of analog applications require an extension of the low-voltage process capabilities towards 12-20 volts or higher for a limited number of pins. The most cost effective way to achieve this is to extend low-voltage sub-micron CMOS processes by the implementation of extended voltage lateral BJT, self-aligned lateral DMOS (LDMOS) and non-self aligned devices with an extended drain, either using existing CMOS process regions (Dolny, G.M. et al., 1986) or by adding a few extra regions. The ESD protection of these high-voltage devices in the low-voltage process presents a new challenge. The most robust way to protect the extended voltage LDMOS devices is by the implementation of a silicon controlled rectifier LDMOS-SCR structure (Concannon, A. et al., 2004). The paper focuses on a device level solution for the control of both the breakdown voltage and the triggering characteristics of the extended voltage ESD devices. This was achieved by the use of super-junctions (multi-RESURF) (Deboy, G. et al., 1998; Xu, S. et al., 2000) and diluted-junctions (Vashchenko, V.A. et al., 2004) widely used for discrete power devices.

Mixed Device-Circuit Solution for ESD Protection of High-Voltage Fast pins

This paper presents a new solution for ESD protection of high-voltage, high-speed pins in power analog circuits, such as switching voltage regulators. The particular implementation consists of a LDMOS-SCR ESD device with the triggering characteristics controlled by an active circuit. Experimental validation of this new approach is provided