Patrice Besse

Efficient TCAD methodology for ESD failure current prediction of smart power ESD protection

This work deals with a method to predict ESD protection robustness with TCAD simulations. Tested on different devices and two smart power technologies, the results are validated with electrical measurement and failure analysis. Failure current is always predicted with a good accuracy compared to technology spreading. In addition, the methodology provides a significant simulation time speedup compared to classical methods based on a temperature criterion.

Identifying electrical mechanisms responsible for functional failures during harsh external ESD and EMC aggression

Abstract For particular applications, system level stresses such as EMC stress or ESD (IEC61000-4-2) are directly applied to the integrated circuits with no external protections. Consequently, the integrated circuits have to be designed for reliability in order to stay alive but also to guarantee the normal operations during severe electrical aggressions. Unfortunately, the simulation of functional failures during severe ESD or EMC events remains very challenging for analog products due the frequency domain and to the high current injection mechanisms. This paper describes a test method to identify the design functions and the physical mechanisms that lead to functional failures when integrated circuits are submitted to system level stress.

Deep Trench NPN Transistor for Low-RON ESD Protection of High-Voltage I/Os in Advanced Smart Power Technology

An innovative self-biased NPN transistor dedicated to the ESD protection of high voltage I/Os is presented. To fulfil a high clamping voltage / low on-state resistance specification, the authors have taken benefit of specific technology features, as deep insulation trenches, low-doped epitaxy and high-doped buried layer. First, the guidelines allowing the increase of the clamping voltage and the lowering of the on-state resistance are defined, based on an accurate description of the physical mechanisms involved during an ESD stress. Then, the proposed NPN transistor is described, and the results of measurements and TCAD simulations are presented. Excellent capabilities as 40 Volt clamping voltage, zero on-state resistance and It2 higher than 5 Ampere have been achieved

Novel method To identify electrical mechanisms responsible for functional failures during Direct Power Injection “DPI”

In particular applications, integrated circuits (ICs) have to be designed to guarantee safe operations during severe electromagnetic aggressions stresses such as Direct Power Injection (DPI). Unfortunately, the simulation of functional failures during DPI events remains very challenging for analogue products due the large frequency domain and to the lack of models for internal parasitic coupling. This paper describes a test method to identify the design functions and the physical mechanisms that lead to functional failures when integrated circuits are submitted to EMC stress.

Development of high-voltage ESD protection devices on smart power technologies for automotive applications

This paper presents two high-performance high-voltage ESD protection devices developed on advanced smart power technologies for automotive applications. The lateral-spacing triggered bi-directional SCR (LSTBSCR) accommodates the requirements and needs of adjustable operation voltage, bi-directional protection, and low DC leakage with varied temperature from -40°C to 175°C. With design optimization, it achieved excellent It2 of 120mA/um, one of the highest reported in literatures. The high-voltage PNP provides desirable non-snapback behavior. A comparison between these two devices was also provided.

TLP-based Human Metal Model stress generator and analysis method of ESD generators

A new setup for generating a Human Metal Model compliant waveform with a TLP is described. To characterize this generator, a new analytical method has been developed, which is applicable to both TLP and HMM and demonstrates fundamental differences between those three types of generators. Results are used to correlate failure levels on active devices.

Hierarchical modeling approach for system level ESD analysis: From hard to functional failure

With the increased number of embedded systems into our surrounding area, the electronic devices are exposed to more severe environments and have to survive ElectroStatic Discharges (ESD). Both hard and functional failures have to be guaranteed. In this paper, we will present the methodology we started to develop eight years ago to predict the impact of (ESD). Through two main examples, we will show that a behavioral modeling of the device can give good simulation results. The next step will be the implementation of failure criteria to predict both hard and functional robustness. This paper is a summary of the various results obtained.