Patricia Desgreys

All-Digital Calibration of Timing Skews for TIADCs Using the Polyphase Decomposition

This brief proposes a new all-digital calibration technique suppressing the timing mismatch effect in time-interleaved analog-to-digital converters (TIADCs) for input at any Nyquist band (NB) using the equivalent polyphase structure of the TIADC. The correction technique is simple and does not require the adaptive digital synthesis filters. The timing mismatch is estimated based on an adaptive stochastic gradient descent technique, which is a promising solution for TIADCs operating at a very fast sampling rate. The digital circuit of the proposed calibration algorithm is designed and synthesized using a 28-nm fully depleted Silicon on insulator (FD-SOI) CMOS technology for the 11-b 60-dB SNR TIADC clocked at 2.7 GHz with the input in the first four NBs. The designed circuit occupies the area of 0.05 mm2 and dissipates the total power of 41 mW.

Nonuniformly Controlled Analog-to-Digital Converter for SDR Multistandard Radio Receiver

A new multistandard radio receiver architecture is presented to take advantage of nonuniformly controlled analog-to-digital converters (ADCs). By defining the statistical parameter related to the random sampling frequency, a time-quantized random sampling scheme is considered to design a nonuniform sampling-based software defined radio (SDR) multistandard receiver. A relaxed design is proposed for an E-GSM/UMTS/IEEE802.11a multistandard receiver. The designed baseband stage avoids the use of the automatic gain control block, relaxes the nonprogrammable antialiasing filter to the third order, and converts data with a 16-bit ADC at a 124-MHz mean sampling frequency.

Pseudorandom clock signal generation for data conversion in a multistandard receiver

In previous work, a non-uniform sampling (NUS) technique to control analog-to-digital conversion (ADC) in a multistandard radio receiver was proposed. In this context of wide band radio signals, the NUS-based ADC offers the advantages of relaxing antialiasing filter (AAF) constraints, decreasing the sampling frequency average and reducing ADC dynamic power consumption. In this paper, we focus on generating non-uniform clock for the sample and hold block of the ADC. The proposed non-uniform clock is based on quantified clock timing. Non-uniform clock is generated from digital control unit (DCU). The DCU is composed of a Gray counter, a linear feedback shift register (LFSR) and a multiplexer to generate specified signals and to select the required clock phase. Simulation results show that performances are similar for conventional uniform sampling (US), additive random sampling (ARS) and time quantized additive random sampling (TQ-RS) for different quantizing factors.

Digital distortion compensation for wideband direct digitization RF receiver

This paper deals with the study of a new correction structure for the distortion compensation in direct digitization receivers. In that purpose, a modified post-distortion algorithm including an efficient adaptive filter is used. Performance have been demonstrated on measurements from a state of the art wideband TI-ADC and from an entire direct-digitization RF receiver. On the TI-ADC, with a two-tone input signal, the algorithm has improved the SFDR by ~ 25dB. Besides, Besides, on the entire receiver, the algorithm has been able to achieve ~ 16dB of improvement on the SFDR.

Beyond 3G wideband and high linearity ADCs

This paper presents the challenges associated to the design of ADCs which must be compliant with 4G/LTE/LTE-A radio requirements. Primarily, the challenges are caused by increasing spectrum bandwidth, multi mode operation and the need of limiting the power consumption in the handset and in the base station. Therefore, wideband converters with high linearity (up to 100 dB of SFDR) and low power consumption (down to 0.5pJ by conversion step) are searched out with possibilities of reconfiguration to deal with the inherent trade-off between all these achievements. The paper gives an overview of the most common ADC architectures to achieve this goal: Flash, Pipeline, Successive Approximation and Sigma Delta ADCs. Then, efficient or still promising techniques are proposed to enhance performance. These techniques are mainly architectural innovations such as continuous time ΣΔ modulators and parallel architectures. The analog circuitry linearity tends to decrease due to the use of new advanced technologies, of increased speed and of simplification dictated by the need of power consumption reduction. However, an increasing use of calibration and digital correction allows both to compensate for the accuracy losses in analog circuitry and to reach higher performance.

Flexible baseband analog front-end for NUS based multistandard receiver

Non-uniform sampling (NUS) controlling baseband analog front-end in a Software Defined Radio multistandard receiver was previously proposed in our works. Non-uniform sampling offers the alias-free sampling feature. Non-uniform sampling based multistandard receiver relaxes Anti-Aliasing Filter (AAF), relaxes automatic gain control circuit and reduces power consumption of the analog-to-digital converter. In this paper, for a finite number of samples, we adopt Bilinskiss theoretical results to multistandard radio signals. The obtained NUS attenuations are relevant to design a flexible AAF. Some comparative AAF orders are presented to figure out NUS advantages in spite of finite number of samples.

Hardware implementation of all digital calibration for undersampling TIADCs

This paper presents a practical implementation of all digital calibration algorithm for the gain and timing mismatches in undersampling Time-Interleaved Analog-to-Digital Converter (TI-ADC). A new Least Mean Square (LMS) based detection scheme is proposed to increase convergence speed as well as to enhance the estimate accuracy. Monte Carlo simulations for a four-channel undersampling 60 dB SNR TI-ADC clocked at 2.7 GHz show that SFDR can achieve approximately 90 dB SFDR within the stable point of the channel mismatch coefficients over the first three Nyquist Bands. The proposed architecture is implemented and validated on the Altera FPGA DE4 board. The synthesized design consumes a few percentages of the hardware resources of the FPGA chip and work properly on a Hardware-In-the-Loop emulation framework.

A fully digital background calibration of timing skew in undersampling TI-ADC

This paper proposes a fully digital calibration of timing mismatch for undersampling Time Interleaved Analog-to-Digital Converter (TI-ADC) employed in Software Defined Radio (SDR) receivers. The proposed calibration scheme employs an ideal differentiator filter, a Hilbert transform filter and a scaling factor to compute the derivative of the input in any Nyquist Band (NB). The efficiency of the proposed technique is shown using a four-channel undersampling 60 dB SNR TI-ADC clocked at 2.7 GHz. Monte Carlo simulations show SNDR and SFDR improvements of respectively, 18 dB and 21 dB over the first three NBs.

Data acquisition test platform for non uniformly controlled ADC

Non Uniform Sampling (NUS) was presented as an emerging solution to reduce aliases for ADC (Analog-to-Digital Converter) in Software Defined Radio receiver. In this paper, practical implementations of NUS, called TQ-RS (Time Quantized Random Sampling) are presented. A test setup for non uniformly controlled data acquisition system is detailed. Experimental results are presented and discussed.

SC and SI techniques performances faced with technological advances [in CMOS]

This paper proposes to compare switched-capacitors (SC) and switched-currents (SI) technique performances faced with technological advances. Three cells of identical low complexity are analysed and the following performance factors are theoretically evaluated: minimal supply voltage, signal input range, static accuracy, maximal sampling rate, signal to noise ratio and power dissipation. Then, a figure-of-merit is formed and its evolution is reported as a function of time. It shows that SI circuits are less sensitive to the supply voltage scaling than SC circuits as long as transistors operate in the strong inversion region. But, as gate-source overdrive is finally reduced with supply voltage, SNR/sub SI/ decreases down to a limit calculated in weak inversion mode.