Chadi Jabbour

All-Digital Calibration of Timing Skews for TIADCs Using the Polyphase Decomposition

This brief proposes a new all-digital calibration technique suppressing the timing mismatch effect in time-interleaved analog-to-digital converters (TIADCs) for input at any Nyquist band (NB) using the equivalent polyphase structure of the TIADC. The correction technique is simple and does not require the adaptive digital synthesis filters. The timing mismatch is estimated based on an adaptive stochastic gradient descent technique, which is a promising solution for TIADCs operating at a very fast sampling rate. The digital circuit of the proposed calibration algorithm is designed and synthesized using a 28-nm fully depleted Silicon on insulator (FD-SOI) CMOS technology for the 11-b 60-dB SNR TIADC clocked at 2.7 GHz with the input in the first four NBs. The designed circuit occupies the area of 0.05 mm2 and dissipates the total power of 41 mW.

Direct delta-sigma receiver: Analysis, modelization and simulation

This paper presents a model of direct delta-sigma receiver (DDSR) and methodology for theoretical transfer function (TF). The theoretical analysis is carried out by modeling the key elements of the DDSR, including the N-path filter, down-conversion mixer, baseband delta sigma modulator (DSM) and FIRDACs in order to optimize the loop filter coefficients. The contribution of different noise sources and the impact of the nonlinearities are also analyzed. The obtained simulation results show the accuracy of the proposed models and method. This top-down approach allows the designer to determine the key parameters for DDSR in terms of noise contributions, nonlinearity impacts, filtering effects as well as gain distribution and thus enables the optimization of the whole receiver. Although this methodology was applied to the conventional DDSR, but it can be used for any receiver architecture based on DDSR.

A flexible direct delta-sigma receiver for GSM/WCDMA/LTE

Direct Delta-Sigma Receiver (DDSR) architecture has emerged as an attractive solution for flexible receivers. In this paper, a reconfigurable DDSR architecture for GSM/WCDMA/LTE standards is presented. A 4th-order DDSR with multi-bit quantizers and reconfigurable sampling frequency is adopted in the design. A maximum gain-control range of 18 dB is employed to respect the dynamic range specifications of the targeted standards. A noise figure of 2.5 dB and a -5 dBm out-of-band IIP3 (OOB-IIP3) are achieved in this design.

A 1 V 65 nm CMOS reconfigurable time interleaved high pass ΣΔ ADC

This paper presents a reconfigurable High-Pass (HP) Time-Interleaved (TI) Delta-Sigma (ΣΔ) Analog-to-Digital Converter (ADC) from theoretical and practical points of view. This ADC is designed to fulfill the requirements of GSM, UMTS, WiFi and WiMAX standards. The reconfiguration is performed by adjusting the interpolation factor, the ΣΔ modulator order and the number of active channels thereby allowing bandwidth-resolution trade-off as well as bandwith-power consumption trade-off. The circuit has been fabricated in a 1 V 65 nm CMOS process. Clocked at 50 MHz, the prototype chip consumes 6 mW per channel and the core die area is 2.52 mm2.

Hardware implementation of all digital calibration for undersampling TIADCs

This paper presents a practical implementation of all digital calibration algorithm for the gain and timing mismatches in undersampling Time-Interleaved Analog-to-Digital Converter (TI-ADC). A new Least Mean Square (LMS) based detection scheme is proposed to increase convergence speed as well as to enhance the estimate accuracy. Monte Carlo simulations for a four-channel undersampling 60 dB SNR TI-ADC clocked at 2.7 GHz show that SFDR can achieve approximately 90 dB SFDR within the stable point of the channel mismatch coefficients over the first three Nyquist Bands. The proposed architecture is implemented and validated on the Altera FPGA DE4 board. The synthesized design consumes a few percentages of the hardware resources of the FPGA chip and work properly on a Hardware-In-the-Loop emulation framework.

A fully digital background calibration of timing skew in undersampling TI-ADC

This paper proposes a fully digital calibration of timing mismatch for undersampling Time Interleaved Analog-to-Digital Converter (TI-ADC) employed in Software Defined Radio (SDR) receivers. The proposed calibration scheme employs an ideal differentiator filter, a Hilbert transform filter and a scaling factor to compute the derivative of the input in any Nyquist Band (NB). The efficiency of the proposed technique is shown using a four-channel undersampling 60 dB SNR TI-ADC clocked at 2.7 GHz. Monte Carlo simulations show SNDR and SFDR improvements of respectively, 18 dB and 21 dB over the first three NBs.

A 65 nm CMOS versatile ADC using time interleaving and ΣΔ modulation for multi-mode receiver

High performances wideband Analog to Digital Converter (ADC) remains a bottleneck to realize software and cognitive radio receivers. Time Interleaved Sigma-Delta (TIΣΔ) architecture is a good candidate to increase the bandwidth of the data converters with the lowest hardware complexity compared to other solutions using parallel sigma-delta modulators. This paper proposes a reconfigurable 4 channels TIΣΔ using the novel GMSCL (General Multi Stage Closed Loop) sigma-delta architecture and a new digital processing reducing considerably the hardware complexity. The sigma-delta modulators have been designed using switched-capacitor technique and implemented with STMicroelectronis 65 nm CMOS technology. Three different scenarios are possible : the first one for GSM standard clocked at 26 MHz and consumes 2.59 mW, the second one for UMTS/DVB-T standards clocked at 208 MHz and consumes 46 mW and the last one for WiFi/WiMax standards clocked at 208 MHz and consumes 92 mW. The total circuit die area is equal to 3 mm2. The digital filtering was validated and synthesized in a 1.2 V, 65 nm CMOS process using VHDL language. For a clock rate of 208 MHz, the evaluated die area is 0.115 mm2.

Optimizing the number of channels for time interleaved sample-and-hold circuits

A technique for optimizing the number of channels for time-interleaved sample-and-hold is proposed. This technique permits to extract the figure of merit of a single sample- and-hold circuit while taking into account the limited gain- bandwidth of a family of operational amplifiers sharing the same topology. A double-sampled architecture of sample-and-holds is used to reduce die area and power consumption. The extracted results allow us to determine the optimal operation frequency and consequently the optimal number of channels for a given sampling frequency required by the time-interleaved sample-and- hold. A demonstration is shown for a gain boosted folded cascode operational amplifier topology in a 65 nm technology.

A LP/HP UMTS/GSM ΣΔ ADC suited for a Zero-IF/Low-IF receiver

This paper presents the design of a reconfigurable Delta Sigma Analog to Digital Converter (ADC). Its main degree of liberty is the choice of the noise shaping among low pass and high pass. This reconfiguration parameter allows it to be adapted for both the Low-IF and the Zero-If receiver architectures. The ADC is GSM/UMTS compliant. It was designed in a 1.2 V 65 nm CMOS process. Electrical simulation results showed a SNDR of 84 dB for the GSM mode with a Low-IF frequency of 19.2 MHz and a SNDR of 77.4 dB for the UMTS at DC.

A low-power ΣΔ ADC optimized for GSM/EDGE standard in 65-nm CMOS

A ΣΔ ADC with both Signal Transfer Function (STF) and Noise Transfer Function (NTF) optimized for GSM/EDGE application is presented. A direct-feedforward single-loop filter is used to improve linearity of the modulator at low supply voltage. From the edge of the signal bandwidth to over 1MHz of band, measured STF is flat and in-band ripple is less than 0.01dB. Clocked @ 26MHz the modulator achieves 82dB dynamic-range, 80dB peak SNR, −85dB peak THD, 88dBc peak SFDR. Implemented in 65-nm CMOS, it consumes 1.74mW from the 1.2V supply and occupies an active die area of 0.081mm2 (395µm×205µm) without voltage references.