Hervé Petit

Reliability aware design of low power continuous-time sigma–delta modulator

Circuit reliability has become a major bottleneck due to ageing degradation. In this paper, reliability-aware methodology and ageing analysis of low power sigma–delta (ΣΔ) modulator are presented. HCI and NBTI are considered as the dominating ageing effects. A second order continuous-time (CT) ΣΔ modulator is implemented for medical application. Ageing estimation is performed at both behavioral and transistor level. Results at behavioral level and transistor level show that the feedback loop in CT ΣΔ modulator is more sensitive and less reliable than the analog loop filter. Comparing with HCI, NBTI is the dominating ageing effect in the designed CT ΣΔ modulator.

CMOS 65 nm wideband LNA reliability estimation

Radio frequency (RF) products are very demanding in terms of technology developments. Reliability will be one of the most important challenges for the semiconductor industry during the following years. This work presents a wideband low noise amplifier (WBLNA) designed in CMOS 65 nm, its model for reliability estimation, and simulated results of fresh and aged devices. The WBLNA failure, defined in this work as the amount of degradation to have 3 dB gain loss or 10% bandwidth reduction, has been found for HCI ID, SBD and EM degradations. The most important simulated reliability degradation results have been highlighted. Therefore, the design for reliability concept can be systematically applied in the RF front-end circuits, and it has helped with WBLNA reliability improvement.

A new synthesis methodology for reliable RF front-end Design

A low power and low cost WLAN/WiMAX RF front-end requires more advanced CMOS technologies whose transistor parameters degradation is becoming worse. Few published works has presented the reliability results for RF circuits. In order to fill this gap, we develop a new synthesis methodology for reliable RF front-end design using the design example of a reliable BLIXER. The first steps of our synthesis methodology is a transistor ageing simulation. Then, we calculate an estimation of the circuit performance and ageing using the circuit design equations and the total derivatives. Thus, we can find the required bias and sizing improving the circuit reliability. The simulation results of the typical circuit are coherent with the WLAN/WiMAX RF front-end specifications. Despite the integrated process variability and mismatch, we observe that 96.4 % of the simulation runs have Gain > 10.0 dB, and 92.1% of the simulation runs have NFmax< 5.0 dB. Moreover, the BLIXER ageing degradation is negligible according to the fitted Poisson distribution of the power consumption for 99.9% of confidence. Going further, we can say that the synthesis methodology proposed and developed for a RF front-end design can be exploited in different AMS/RF circuits and also generalized for a single bottom-up reliable-system design approach.

AMS and RF design for reliability methodology

The design for reliability concept is already in use on digital circuits, but not systematically in use on AMS or RF circuits. A reliable circuit design demands knowledge of the physical degradation and models to analyze the reliability in earlier stages. Also, it needs to be simple enough to be used on the redesign. In this work, we propose and validate an AMS and RF circuit design for reliability method. In order to investigate our method, we have designed a 5–3 NOR interpolative Digital Controlled Oscillator (DCO) near 1 GHz applications. This design example has presented 1.4% decrease of oscillation frequency, 0.2% decrease of phase noise for a 1 MHz off-set, and 2.1% decrease of power consumption after 10 years of degradation. According with the trends presented in Table I, we estimate that the fosc ageing degradation was improved of 13 % by applying the design for reliability method.

A general cost-effective design structure for probabilistic-based noise-tolerant logic functions in nanometer CMOS technology

Noise-immunity of a logic gate or a circuit is now an important design criterion with dimension scaling to nanometers. Two noise-immune design structures based on Markov random field (MRF) have been proposed in [1], [2] and [3]. These design structures can achieve an excellent noise-immunity but with a large number of redundant transistors. In this paper, a general noise-immune design structure easy to implement has been proposed. It can achieve nearly the same noise-immunity as Master-and-Slave MRF (MAS MRF) [3] but with a significantly less area penalty. Basic logic gates are simulated and comparison of different circuits based on different design structures is presented. These simulations are based on the Berkeley Predictive Technology Model (BPTM) 65nm CMOS Technology [4] and ST 65nm CMOS models.

Statistical analysis of noise in broadband and high resolution ADCs

The estimation of mismatch-induced errors between the channels of a Time-Interleaved ADC is crucial for implementing an efficient calibration method. This step is often done with the assumption that all the noise sources have a white gaussian distribution. In this paper we analyze the statistical properties of noise components in wideband ADCs in terms of Probability Density Function (PDF) and Power Spectral Density (PSD) and discuss some conditions of whiteness.

Simulation methodology for large-bandwidth Track-and-hold microwave circuit

A step-by-step simulation methodology for large-bandwidth Track-and-hold (T/H) microwave circuit is proposed. A T/H circuit is characterized accurately under the Cadence© environment. With the consideration of a specific windowing function, linearity simulation analysis could be done effectively. Moreover, the use of an input frequency generation function, in accordance with theoretical calculation, allows to treat the entire input bandwidth (BW). A simulated switched emitter follower (SEF) structure in a 0.13-μm SiGe BiCMOS technology with 24 GHz effective bandwidth and a 4 GS/s clock illustrates our methodology.

A synthesis methodology for AMS/RF circuit reliability: Application to a DCO design

Circuit ageing degradation is becoming worse in advanced technologies, while application fields like military, medical and energy demand more reliability. Thus, reliability is one of the most important challenges of the semiconductor industry [1]. In this work, we review the physical ageing phenomena, their simulation model, and how they can be avoided. Then, we propose a synthesis methodology composed of classical circuit optimization with the reliability analysis in earlier stages. Also, the variability of the integration process technology is taken into account. We compare a classical and a reliable designed digital controlled oscillator (DCO) in order to show a reduction of 16% in the oscillation frequency ageing degradation. In this way, the reliable design makes the circuit lifetime five times longer, if we fix the maximum frequency ageing degradation at 2.0%. Finally, we present the reliability as a design criterion, advantages and disadvantages of our methodology.

Merged Digitally Controlled Oscillator and Time to Digital Converter for TV band ADPLL

In this paper we present a merged Digitally Controlled Oscillator DCO and Time To Digital Converter TDC architecture. The DCO is a nine-stage interpolative ring made by NOR cells. It is designed for TV applications and it is implemented in 65nm CMOS process. The oscillator has a large frequency range, from 50MHz to 500MHz, and a 28 × 39/Ltm2 core area. It consumes 1mA from 1.2V power supply, and it has −120dBc/Hz@5MHz phase noise for 420 MHz carrier frequency. The oscillator states are directly used to measure the delay between input and output clocks. The resulting TDC is compact, very economic in power consumption and it has a resolution that is equal to 1/18 of the oscillation period. The DCO and the TDC are used in an All Digital Phase Locked Loop ADPLL.

Compressed sensing for astrophysical signals

In order to reduce power consumption and limit the amount of data acquired and stored for astrophysical signals, an emerging sampling paradigm called compressed sensing (also known as compressive sensing, compressive sampling, CS) could potentially be an efficient solution. The design of radio receiver architecture based on CS requires knowledge of the sparsity domain of the signal and an appropriate measurement matrix. In this paper, we analyze an astrophysical signal (jovian signal with a bandwidth of 40 MHz) by extracting its relevant information via the Radon Transform. Then, we study its sparsity and we establish its sensing modality as well as the minimum number of measurements required. Experimental results demonstrate that our signal is sparse in the frequency domain with a compressibility level of at least 10%. Using the Non Uniform Sampler (NUS) as receiver architecture, we prove that by taking 1/3 of samples at random we can recover the relevant information.