Patrick H. Buffet

Methodology for I/O cell placement and checking in ASIC designs using area-array power grid

Electrical rule checking is fundamental to achieve a good I/O cell placement. This paper presents the analysis techniques used to design a robust power-grid structure, the method used to make I/O cell placement guidelines, details of the I/O cell placement process and electrical checking algorithms.

Issues and strategies for the physical design of system-on-a-chip ASICs

The density and performance of advanced silicon technologies have made system-on-a-chip ASICs possible. SoCs bring together a diverse set of functions and technology features on a single die of enormous complexity. The physical design of these complex ASICs requires a rich set of functional elements that integrate efficiently with a set of design flows and tools productive enough to meet product requirements successfully, without consuming more time or design resources than a simpler design. The architecture described, including functional libraries and physical design conventions, enables the creation of multiple SoC ASIC designs from a common infrastructure that addresses silicon integration, electrical robustness, and packaging challenges. An implementation strategy follows from this design infrastructure that includes hierarchical design concepts, placement, routing, and verification processes.

The first copper ASICs: A 12M-gate technology

This paper describes the first CMOS ASIC logic family built with copper metallurgy. Chips with up to 12-million equivalent gates can be designed in the 0.16 /spl mu/m process. The technology, product characteristics, CAD system and first customer chips are discussed.