Timothy W. Budell

The effects of on-chip and package decoupling capacitors and an efficient ASIC decoupling methodology

This paper presents an in-depth analysis of the effectiveness of on-chip and package decoupling capacitors in light of the interaction between chip-package resonance and the frequency content of switching sources, and suggests an approach for decoupling analysis in fast turn-around ASIC designs, achieving both simulation efficiency and accuracy. The analysis is based on accurate modeling of the on-chip and package power supply structures of ASIC flip-chip modules as distributed networks to provide precise understanding of switching noise mechanisms in distributed power supply structures in both the time and frequency domains. The simulation efficiency versus accuracy of two types of package models is discussed. The local effectiveness of on-chip and package decoupling capacitors is illustrated using detailed, frequency-domain impedance profiles of the on-chip and package power supply networks, demonstrating location-dependant responses that vary according to the local placement of decoupling capacitors. Based on the study, a methodology is presented for accurately determining the quantities and locations of on-chip decoupling capacitors required to limit on-chip transient power supply collapse to a pre-defined level.

Comparison of multilayer organic and ceramic package simultaneous switching noise measurements using a 0.16 /spl mu/m CMOS test chip

This paper presents a comparison of simultaneous switching-output noise measurements taken with a 0.16 /spl mu/m CMOS test chip on two flip-chip multilayer packages: IBMs new HyperBGA/sup TM/ high-density PTFE-based organic BGA, and an existing IBM ASIC-menu alumina-ceramic BGA. In two classes of tests, measured transmitted noise from the organic BGA was found to average less than half that of the ceramic BGA. Technology and design features of the chip and package test vehicles are described and compared. Several types of simulations, including extracted loop inductance and full-wave simulation of coupling parameters, identify various noise components in each package and elucidate the large differences in measured noise between the two packages.

Comparison of simultaneous switching noise measurements using netlist compatible multilayer ceramic packages having variously compromised reference planes

This paper presents a comparison of simultaneous switching-output noise and skew measurements taken with a 0.12 /spl mu/m CMOS test chip on three flip-chip, multilayer-ceramic, single-chip modules (SCMs) having differing amounts of reference mesh and power-supply vias in the package under the chip outline. Missing reference mesh equates to poor current-return paths for signals traversing such package regions. Missing power-supply vias equate to increased supply inductance. The test chip has 732 individually programmable off-chip output buffers, each of which can be individually probed. The first package has full reference mesh under the chip. The second package has reference mesh only in the upper half of the package under the chip. The third package has essentially no reference mesh under the chip. Technology and design features of the chip and package test vehicles are described. Noise and delay measurement techniques and results are presented. The large number of off-chip output buffers enables a statistical view of transmitted noise and skew behavior as signal current-return paths are compromised. This analysis is graphically presented and discussed. Several types of simulations, including extracted loop inductance and full-wave simulation of coupling parameters, are presented. These simulations elucidate the large differences in measured transmitted noise and off-chip output buffer skew between the three packages.

Accurate HSPICE modeling of arbitrary package geometries using transmission-line equivalent techniques

Arbitrary package geometries can he converted into accurate high-speed transmission line equivalent circuits using standard equations for characteristic impedance, plate capacitance, and unit delay. Constructing the correct transmission-line topology requires an understanding of how the skin effect alters high-speed electromagnetic field propagation within a microelectronic structure. Using such transmission-line techniques, this paper examines io detail the high-speed electrical behavior of a number of common package structures, including signal vias in single-ended and differential stripline and microstrip configurations; singleended and differential signal wires passing over gaps in microstrip or stripline reference planes; and single- and dualreference stripline systems. These bansmission line representations can be readily simulated with any HSPICE or equivalent circuit simulation engine. These techniques are then applied to the packages and hardware data presented in [l]. It is shown that the noise measurements of the package having the most severely compromised reference mesh and power-supply vias under the die are dominated by cavity noise. I. Introduction