C. S. Premachandran

A two axes scanning SOI MEMS micromirror for endoscopic bioimaging

A novel silicon on insulator (SOI) MEMS process has been designed and developed to realize a two axes thermally actuated single crystal silicon micromirror device, which consists of a mirror plate, four flexural springs and four thermal actuators. The mirror plate has the same thickness as a SOI device layer i.e. 4 µm. The SOI layer is selectively thinned down to 2 µm for fabricating flexural springs and thermal actuators. The thinning of the SOI layer is essential to lower (control) the flexural rigidity of the springs and the actuators and thus to achieve a higher tilt angle at low thermal power. The developed single wafer process is based on dry reactive ion etching CMOS compatible chemistries. The minimum chip size design of 1 mm × 1 mm has a 400 µm diameter mirror plate. Other chip designs include the mirror diameters in the range from 200 to 500 µm. This paper also presents a study on the mirror plate curvature, thermal actuation mechanism and the experimental results. The measured maximum angular deflection achieved was 17° at an operating applied voltage of less than 2 V, and the radius of curvature of the mirror plate was in the range from 20 to 50 mm. The micromirror was developed for a miniature catheter optical probe for optical coherence tomography in vivo imaging. A low cross-sectional size of the probe and higher resolution are essential for investigating inaccessible pathologies in vivo. This required a compact micromirror chip and yet sufficiently large mirror plate (typically ~500 µm or more), this trade-off was the key motivation for the research presented in this paper.

Design and development of a 3D scanning MEMS OCT probe using a novel SiOB package assembly

A MEMS optical coherence tomography (OCT) probe prototype was developed using a unique assembly based on silicon optical bench (SiOB) methodology. The probe is formed by integrating a three-dimensional (3D) scanning micromirror, gradient refractive index (GRIN) lens and optical fiber on SiOB substrates having prefabricated self-aligned slots. The two-axis scanning micromirror is based on electrothermal actuation with required voltage less than 2 V for mechanical deflections up to 17°. The optical probe was enclosed within a biocompatible, transparent and waterproof polycarbonate tube with a view of in vivo diagnostic applications. The diameter of the miniature probe is less than 4 mm and the length of its rigid part is about 25 mm. The probe engineering and proof of concept of the probe were demonstrated by obtaining en face and three-dimensional OCT images of an IR card used as a standard sample.

Development of novel intermetallic joints using thin film indium based solder by low temperature bonding technology for 3D IC stacking

Low temperature bonding technology was developed using In-alloy on Au at a low temperature below 200 °C forming robust intermetallics (IMC) joints with high remelting temperature (≫300°C), so that after bonding, the IMC joints can withstand the subsequent processes without any degradation. Process parameters on the solder joint were optimized extensively in bonding and annealing process (temperature, time, and pressure). The joint fabricated at an optimal condition, which is 180°C for 45sec followed by annealing at 120°C for 12hrs, was evaluated in terms of microstructure and compositional observations by means of scanning electron microscope (SEM) and transmittance electron microscope (TEM). As a result, it was confirmed that the joint was completely occupied with the Au-In based IMC phases. And the re-melting temperature was measured as above 400°C by using Differential Scanning Calorimetery (DSC) and Thermo-Mechanical Analysis (TMA). This IMC joint showed a high bonding shear strength (≫20MPa) and a low electrical resistance (≪100mΩ). Based on this study, the 3 stacked dice with 8×8 mm2 dies with ∼1700 I/Os of 80um solder bumps were fabricated in a chip to chip stacking method. It showed uniform bonding all over the die in each layer and the high bonding strength of ∼40 MPa and passed the 3 times reflow test at 260 °C. The IMC joint reliability was examined. After going through the multiple reflows at 260°C, the bonded samples exhibited no delaminating and no changes in the bonding strength and the electrical resistance.

Vacuum packaging development and testing for an uncooled IR bolometer device

A vacuum package has been developed for 128/spl times/128 array IR bolometer device with Ge window having anti reflection (AR) coating. For a good vacuum package hermeticity and low out gassing are the two critical elements. A good hermetic sealing has been achieved with Ge window attachment using solder bonding. Different metallization structures have been tried and metallization of oxide/Ti/Ni/Au with additional annealing process was found to have good adhesion and solder wetting. Getters have been activated before final vacuum sealing of the package to absorb the outgassing gases from the packaging materials. Residual Gas analysis (RGA) showed that Thermo electric cooler used inside the package outgassed more compared to other materials. Vacuum inside the package was measured by using a single element IR bolometer device and found to have vacuum of 50milli torr. The developed vacuum package has been tested functionally and found to be no degradation in image before and after packaging.

A novel, wafer-level stacking method for low-chip yield and non-uniform, chip-size wafers for MEMS and 3D SIP applications

Stacking of wafers with low chip-yield and non uniform chips size is developed for MEMS and 3D packaging applications. Stacking of MEMS and ASIC wafers one over other is difficult due to difference in chip yield and chip size. A cap wafer which is used for sealing the MEMS wafer in the wafer level package (WLP) is used for stacking the known good dice from MEMS wafer. Cavities and through silicon vias (TSV) are formed on a support wafer which matches with the ASIC (electronics) wafer. Based on the mapping of the ASIC wafer, a known good die from MEMS wafer is picked and attached into the support wafer. MEMS devices are attached in to the support wafer either by face down or face up with respect to ASIC chip. Redistribution lay outs are made on the ASIC wafer to match the pads configuration of the MEMS and ASIC wafer. The completed support wafer with MEMS devices in the cavity is bonded with ASIC wafer in a wafer bonder for final assembly. Since through hole vias are formed on the support wafer there is no need to etch through silicon via on either MEMS or AISC wafer. A hermetically sealed MEMS chip with ASIC one over other is assembled to meet the final real estate reduction of the package size. A stacking approach for low yield and non uniform chip size wafers is demonstrated.

C2W bonding method for MEMS applications

A low temperature C2W (Chip to wafer) bonding method is developed for integrating MEMS and electronics into a wafer level package. The diced known good MEMS chip is picked and bonded onto an ASIC wafer using an In based low temperature solder below 200 degC. The C2W bonded MEMS and ASIC wafer is sealed with a cap wafer. The sealed package is characterized for hermeticity and shear strength and found to meet the minimum requirements for a good sealing and bonding.

Development of a Disposable Bio-Microfluidic Package With Reagents Self-Contained Reservoirs and Micro-Valves for a DNA Lab-on-a-Chip (LOC) Application

A disposable self-contained microfluidic package has been developed and tested for on-chip DNA extraction from human blood for practical lab-on-a-chip platform. The microfluidic package has been customized to allow easy interface between the microscale sample injection to the Si-based microscale sample preparation chip. For precise sample dispensing and to minimize dead volume and/or sample lost conical-shaped reservoirs have been employed. Reservoirs filled with reagents are sealed by a highly elastic thin rubber membrane. Automated actuation system has been designed and implemented for programmable sample/reagent dispensing using thin rubber membrane-plunger mechanism. The packaged DNA chip has been tested using blood sample and the testing protocol has been optimized to meet the requirements for DNA extraction.

Design, process integration and characterization of wafer level vacuum packaging for MEMS resonator

This paper discusses wafer level vacuum sealing technology with evaporated AuSn solder for a microelectromechanical systems (MEMS) resonator without getter material. The MEMS resonator is fabricated and characterized in a vacuum chamber. Relationship between the Q-factor of the MEMS resonator and the vacuum level is established and used as a reference for later vacuum level calibration. Wafer bonding using evaporated AuSn solder is performed in an EVG wafer bonder. With optimized bonding conditions, the achieved shear strength is higher than 59 MPa and uniform cross-section of the bonding ring has been achieved. The calculated He leakage rate is between 10−13 atm cc/s and 10−14 atm cc/s. By comparing the measured Q-factor of packaged resonator with the reference curve, the corresponding vacuum level is 0.2 Torr. Reliability tests results show that shear strength decreases for 7% and still high enough for real application. The vacuum level after reliability tests is comparable to that of long term vacuum level.

Fabrication and Testing of a Wafer-Level Vacuum Package for MEMS Device

A wafer-level vacuum package with getters deposited on the cap wafer is developed for an accelerometer device. An accelerometer wafer and cap wafer is bonded together in a vacuum of 1 mtorr and is characterized using a micro-electro-mechanical systems (MEMS) motion analyzer (MMA). Vacuum inside the package is measured indirectly by measuring the Q-factor response of the accelerometer structure inside the package. The obtained results indicated that there is variation from the center to the edge of the wafer. This may be due to difference in the outgassing of the package. Different reliability tests on the wafer-level package showed the package is robust to the reliability conditions. A progressive test on the Q-factor for different cycles of reliability test proved that there is no shift in the measurement value. A 3-D wafer-level package for accelerometer device is also developed to meet the requirements of vacuum packaging. Hermeticity and CV test showed no degradation in the device performance when subjected to reliability tests.

Design and Development of Fine Pitch Copper/Low-K Wafer Level Package

Copper/Low-k structures are the desired choice for advanced integrated circuits (ICs) as the IC technology trends moving toward finer pitch, higher speed, increased integration and higher performance ICs. Copper interconnects with low-k dielectric material improves the ICs performance by reducing interconnect RC delay, cross talk between adjacent metal lines and power loss. However, low-k materials have intrinsically lower modulus, lower fracture toughness and poorer adhesion compared to the traditional silicon dioxide (SiO2) and silicon nitride (SiN) dielectric material. Thus, The packaging of Cu/low-k IC device is a challenge for packaging industry to integrate these device with out failure during assembly and reliability. More over these advanced high performance ICs requires high density fine pitch off-chip interconnects. Wafer level packaging is one of the promising candidates for the future fine pitch and high performance Cu/Low-K ICs packaging as it can accommodate the high density fine pitch off-chip interconnects at low cost. This work presents, the detailed parametric study to optimize the chip level and package level reliability and wafer level packaging (WLP) process, assembly and package reliability assessment of the Cu/Low-K devices using finite element model (FEM) analysis. To evaluate the Cu/Low-K WLP reliability, 7 mm x 7 mm size die is designed with 128 Input/output off-chips interconnects at 300 mum pitch in two depopulated rows. Test vehicles are fabricated on 200 mm diameter wafer with 15 layers blanket black diamond Low-K stack with one final Cu metal and Al bond pad. Two different Pb free solder interconnects, thick copper column of 100 mum height with SnAg solder cap and SnAg solder bump of 150 mum height with 5 micron thick copper UBM, are fabricated. The Cu/low- K test dies are assembled onto a 2 layer high Tg FR-4 substrate using 2 different types of no-flow underfill to assess the reliability of this Cu/Low-K WLP, various JEDEC standard reliability tests are carried out and failure analysis also performed.