Patrick Knebel

HP's PA7100LC: a low-cost superscalar PA-RISC processor

Describes a new low-cost, superscalar PA-RISC processor including two integer arithmetic and logic units, a floating-point coprocessor, and a memory and I/O controller on a single VLSI chip. It implements the full PA-RISC1.1 functionality and adds several new features, including little-endian capability, uncacheable memory pages, and new multimedia instructions. The chip is fabricated in 0.8- mu m, three-level metal CMOS and is designed to run from 0 to 75 MHz. The cache system consists of an off-chip combined instruction/data cache ranging from 8 kByte to 2 MByte and a small on-chip instruction buffer. Memory consists of 4 MByte to 2 GByte of standard DRAMs or SIMMs (single in-line memory modules) connecting directly to the processor chip. The chip achieves performance levels comparable to those of previous generation high-end workstations while lowering overall system cost and power consumption to make possible a new generation of low-cost systems.<<ETX>>

A 90 MHz CMOS RISC CPU designed for sustained performance

A CMOS CPU which operates at 90 MHz under typical conditions and implements an existing RISC (reduced-instruction-set-computer) 140-instruction set is described. The processor has been designed for sustained performance for workstation and both commercial and technical multiuser applications. Key performance features include a 3-ns, 32-b adder; low-skew on-chip clock buffers; and cycling off-chip caches at the operating frequency, using industry-standard synchronous static random-access memories (SRAMs). The speeds obtained are comparable to those of many emitter-coupled logic (ECL) implementations. The CPU chip includes the following hardware: integer fetch and execute unit, on-chip split I/D TLBs (translation lookaside buffers) with two-way 64 entries each, control for second-level off-chip TLBs, control for off-chip two-way split I/D writeback caches with single-bit error correction for data, full multiprocessing support hardware, inference for performance analysis and tuning, and a tightly coupled coprocessor interface.<<ETX>>