Patrick P. Siniscalchi

A 450 Mb/s analog front-end for PRML read channels

The high user densities and data rates supported by todays hard-disk drives (HDD) demand complex read channel ICs. High-performance analog front-end (AFE) circuits provide automatic gain control (AGC), programmable band limiting and pulse shaping prior to signal sampling and further processing of the data in the digital domain. A 450 Mb/s analog front-end, integrated into a 16/17 code rate EPR4 read channel, contains an AGC loop, which includes a programmable gain stage (PGA), an exponential variable-gain amplifier (VGA), a 7/sup th/-order 120 MHz lowpass filter (LPF), an active dc offset cancellation circuit, and digital feedback. Utilizing multilevel qualification and a variable loop time constant, the AGC acquires a 12 dB gain change within 5 data bytes. Thermal asperity (TA) and amplitude asymmetry compensation make the analog front-end ideally suited for magnetoresistive (MR) head-based applications. Implemented in 5V/3.3V dual voltage 0.35 /spl mu/ BiCMOS, the complete circuit occupies 2.29 mm/sup 3/ and dissipates 232 mW.

A 20 W/Channel Class-D Amplifier With Near-Zero Common-Mode Radiated Emissions

A class-D amplifier that employs a new modulation scheme and associated output stage to achieve true filter-less operation is presented. It uses a new type of BD modulation that keeps the output common-mode constant, thereby removing a major contributor to radiated emissions, typically an issue for class-D amplifiers. The amplifier meets the FCC class B standard for radiated emissions without any LC filtering. It can accomplish this without any degradation to audio performance and while retaining high efficiency. THD+N is 0.19% at 1 kHz while supplying 5 W to an 8 Ohm load from a 12 V supply. Efficiency is 90% while providing 10 W under the same supply and load conditions. The new output stage occupies 1.8 mm2 per channel using the high voltage devices of a 0.25 ¿m BCD process.

A 20W/channel Class-D amplifier with significantly reduced common-mode radiated emissions

Due to their rail-to-rail switching nature, Class-D audio amplifiers are prone to generating electromagnetic interference (EMI) that is in excess of what is acceptable in many systems. Such systems typically require devices to limit their EMI to an accepted standard, such as the FCC Class-B standard. In Class-D audio amplifiers that employ Class-BD modulation [1] using a single supply, the common-mode output signal, VCM, has a significant EMI component because this signal also swings rail-to-rail at the amplifier switching frequency, typically in the hundreds of kHz. This phenomenon is illustrated in the upper signals of Fig. 26.4.1.

A CMOS ADSL codec for central office applications

A CMOS central office codec that supports Full Rate and G.Lite asymmetric digital subscriber line (ADSL) transmission is described. The transmit channel consists of application-dependent digital filters, a 14-bit, 8.832-MSample/s current steering DAC, a 1.104-MHz analog filter, and a programmable attenuator. Due to extensive on-chip digital signal processing, the codec complies with the ADSL transmit power spectral density standards without external filtering. The receive channel contains -17.5 to 33.5 dB of programmable gain staggered strategically across three stages, a 138-kHz analog low-pass filter, a 14-bit, 2.208-MSample/s pipeline ADC, and a digital 138-kHz low-pass filter. The receive channel has a wide input range that can accommodate large line voltages present at the line hybrid circuit. The IC occupies 55.2 mm/sup 2/ and dissipates 450 mW from a 3.3-V supply.

High-precision, programmable 1-10 MHz bandwidth, 0-20 dB gain communication channel for digital video applications

The analog signal processing portion of a digital video demodulation scheme is built in a 5 V BiCMOS process. The channel is both cutoff frequency and gain programmable from 1/spl rarr/10 MHz and 0/spl rarr/20 dB, respectively. The filter is realized as a 4/sup th/ order Gm/C Butterworth lowpass and includes in-package trim for accurate control. A programmable gain amplifier is placed in front of the filter for better S/N performance (>40 dB) and lower intermodulation distortion (>-52 dB). The PSRR of this single-ended channel is better than 40 dB. The channel dissipates 250 mW.

A voice processing and control module for cable telephony applications

An IF-baseband multi-chip module, fabricated in 3.3V 0.35/spl mu/m mixed-signal and 1.8V 0.18 /spl mu/m digital CMOS provides OQPSK demodulation with carrier recovery, memory and control, voice-companding codecs, and SLIC interfaces (SIs) for a CATV telephony distribution system. The die area of the mixed-signal IC is 84.9mm/sup 2/ and 15.2mm/sup 2/ for the digital IC. The power dissipation is 660mW.

S/N Optimized, Programmable 1–10 MHz Bandwidth and 0–20 dB Gain, Precision I-Q Communication Channel for Digital Video Applications

An analog part of a digital-video quadrature demodulation scheme is built using a 7 GHz, 0.8 μm biCMOS process. The scheme provides for 1–10 MHz cutoff frequency and 0–20 dB gain controls and dissipates 250 mW from a power supply of 5 V. The channel filtering is realized by two identical 4th Order Butterworth lowpass filters built with the gm-C technique. They are equipped with cutoff programming and in-package trim tuning for cutoff adjustment. A programmable gain amplifier is placed in front of each filter for better joint noise and intermodulation performance. Such an arrangement allows to operate the filter at a maximum signal level improving the worst-case channel S/N by 6.5 dB. For the in-band components the worst case S/N is better than 41 dB, whereas THD and IMD are less than −48 dB. This single-ended channel achieves PSRR of 42 dB.