Patrick Thompson

Chip-scale packaging

Uniting the advantages of bare die and mainstream packaging, these minimal IC supports are racing to the aid of portable yet powerful products. Rigorously defined, the perimeter of such a package is no more than 1.2 times the perimeter of the die it contains, so that few other IC packages are any smaller. This reduction in size is the key driver of the popularity of the approach. But because the term chip-scale has a marketing value, some manufacturers have extended it to cover other sizes, too. Chip-scale packaging technology is still taking its first steps into the marketplace, and issues of standards, design, and reliability remain to be solved. Even so, an infrastructure for the technology is beginning to develop, and its potential market seems to be guaranteed, not least by consumer thirst for portable electronic applications, for which the small, light package is a natural.

Stencil printing process development for low cost flip chip interconnect

Traditional methods for forming flip chip interconnection include evaporation and electroplating. While both options have proven performance records, their costs are too high for many of todays cost-sensitive applications. Motorola AISL (Advanced Interconnect Systems Laboratory) developed a low cost flip chip interconnect alternative, which electroless plates Ni/Au as the under bump metallurgy (UBM), deposits solder paste using a stencil or photoresist mask, and reflows the paste to form solder bumps. This paper is focused on the stencil print process development for wafer solder bumping. Solder paste selection, characterization, stencil design, and process parameter optimization are critical factors for successful fine pitch stencil printing. Fine mesh eutectic solder pastes (Type 5: -500+635, Type 6: -635) with different flux vehicles were evaluated for printability and reflow studies. Paste and flux modification and co-development with vendors for this specific application were conducted. An optimal paste, with specified viscosity and desired print, reflow and cleaning behavior, was developed. Wafer stencil design rules were established to deposit the right amount of solder paste to form the required reflowed solder bump height without bridges between pads. Printing and reflow design of experiments were performed to establish the baseline and optimum process parameters. Solder bump characterizations, including bump height and uniformity, composition, shear force, and SEM bump profile and cross section microstructure analysis, were conducted. Development and characterization results are presented.

Reliability characterization of the SLICC package

SLICC (Slightly Larger than IC Carrier) is a chip-scale ball grid array (BGA) package currently under development at Motorola. The SLICC package consists of a solder-bumped integrated circuit (IC) which is flip-chip bonded to an interposer substrate-approximately 8 mils thick-and then underfilled with an encapsulant. Chip I/Os are routed to package I/Os through plated through holes (PTHs) in the interposer substrate. Package I/Os are composed of solder bumps (approx. 22.2 mils in diameter on a 32-mil pitch) attached to the bottom side of the interposer substrate. The most apparent benefit of the SLICC package is its utilization of the area efficiency associated with direct chip attach (DCA) technology, coupled with the assembly, test, and repair simplicity afforded by BGA-type packaging.

Reliability development and qualification of a low-cost, PQFP-based MCM

In Motorolas experience with commercial MCM customers, cost reduction is the largest driving factor for interest in MCMs. Speed and other performance factors are of secondary interest. Development and qualification can add significantly to the total cost of an MCM, so in addition to the normal desire to provide reliable products, the cost of doing so has gained increased importance. Motorola has identified three key factors in providing cost-effective MCMs: leverage single chip package experience, qualify MCM product families (package types), and use only qualified silicon devices in MCM products. This paper describes application of the three key factors to the reliability qualification of the 28 mm MCML Series package, a PQFP- (Plastic Quad Flat Pack) based MCM. An initial reliability evaluation was performed to investigate reliability issues. Subsequent to the results of the initial evaluation, changes were made to assembly processes and materials. The MCM was then submitted to a suite of reliability stresses selected to evaluate mechanical, thermomechanical, moisture and longevity performance. The MCM passed electrical and visual (SAT, or Scanning Acoustic Tomography) reliability requirements for all stresses, and performed well in extended stress tests as well. A procedure is in place to help insure high reliability for subsequent products in the 28 mm PQFP MCM package.<<ETX>>

Flip-chip BGA assembly process and reliability improvements

Chip scale packages (CSP) are entering large-scale production in applications such as portable computers and consumer products. In such applications, size and weight reduction is a key goal. However, because the bulk of present and near-term CSP applications are cost-sensitive, these size and weight reductions can not come at a premium cost. The CSP producer is faced with a multi-faceted challenge. State-of-the-art process, equipment and materials are required to build these packages, but little to no price increase is acceptable. By their nature, CSPs contain minimal material to provide mechanical and environmental protection to the semiconductor die, yet no reliability performance relief is granted to CSPs. In this paper, the efforts to meet the CSP metrics of low size and weight, low cost, and high reliability for a flip-chip BGA package (the SLICC, or Slightly Larger than IC Carrier) are presented. For this package, the key challenge was to improve reliability from the then-present unacceptable level to meet Motorola package reliability requirements, without causing an unacceptable penalty in cost or manufacturability. The package construction and assembly are reviewed. Project success metrics are presented. The rational, planning, execution and analysis of a series of designed experiment performed to improve manufacturability and/or reliability are explained. The success of efforts in meeting cost and manufacturability metrics while exceeding reliability metrics is described.

MCM-L product development process for low-cost MCMs

System size and cost reduction are often the largest factors for interest in commercial MCMs. Performance improvement is generally of secondary interest. Development and qualification can add significantly to the total cost of an MCM, so in addition to the normal desire to provide reliable products, the cost of doing so has gained increased importance. A new product introduction (NPI) process for low-cost MCMs has been implemented to rapidly provide cost-effective, reliable MCM solutions for cost-sensitive MCM users. The NPI process is based on three attributes: leverage single chip package (SCP) experience and technology, perform product family qualifications, and use only previously qualified silicon in MCMs. Application of the NPI process to the development and qualification of a 28 mm PQFP (Plastic Quad Flat Pack)-based MCM package is presented in this paper. >