Vincent Nollet

Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip

The ability to (re)schedule a task either in hardware or software will be an important asset in a reconfigurable systems-on-chip. To support this feature we have developed an infrastructure that, combined with a suitable design environment permits the implementation and management of hardware/software relocatable tasks. This paper presents the general scope of our research, and details the communication scheme, the design environment and the hardware/software context switching issues. The infrastructure proved its feasibility by allowing us to design a relocatable video decoder. When implemented on an embedded platform, the decoder performs at 23 frames/s (320/spl times/240 pixels, 16 bits per pixel) in reconfigurable hardware and 6 frames/s in software.

Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles

Run-time management of both communication and computation resources in a heterogeneous network-on-chip (NoC) is a challenging task. First, platform resources need to be assigned in a fast and efficient way. Secondly, the resources might need to be reallocated when platform conditions or user requirements change. We developed a run-time resource management scheme that is able to efficiently manage a NoC containing fine grain reconfigurable hardware tiles. This paper details our task assignment heuristic and two run-time task migration mechanisms that deal with the message consistency problem in a NoC. We show that specific reconfigurable hardware support improves the performance of the heuristic and that task migration mechanisms need to be tailored to on-chip networks.

Designing an operating system for a heterogeneous reconfigurable SoC

The emerging need for large amounts of flexible computational power on embedded devices motivated many researchers to incorporate reconfigurable logic together with an instruction-set-processor (ISP) into their architectures. This implies that tomorrows applications will make use of both the ISP and the reconfigurable logic in order to provide the user with maximum performance. Today, however, a few stumbling blocks prevent these kinds of heterogeneous architectures from becoming mainstream. The technology still lacks a form of run-time management infrastructure. This infrastructure should ease application development by shielding the programmer from the complexity of the system and by providing a clear application development API. This paper presents a novel approach for designing an operating system for reconfigurable systems (OS4RS). Creating such an operating system is an integral part of our ongoing research regarding reconfigurable computing. An initial version of our operating system was used to manage a reconfigurable systems demonstrator.

Operating-system controlled network on chip

Managing a Network-on-Chip (NoC) in an efficient way is a challenging task. To succeed, the operating system (OS) needs to be tuned to the capabilities and the needs of the NoC. Only by creating a tight interaction can we combine the necessary flexibility with the required efficiency. This paper illustrates such an interaction by detailing the management of communication resources in a system containing a packet-switched NoC and a closely integrated OS. Our NoC system is emulated by linking an FPGA to a PDA. We show that, with the right NoC support, the OS is able to optimize communication resource usage. Additionally, the OS is able to diminish or remove the interference between independent applications sharing a common NoC communication resource.

Highly scalable network on chip for reconfigurable systems

An efficient methodology for building the billion-transistors systems on chip of tomorrow is a necessity. Networks on chip promise to be the solution for the numerous technological, economical and productivity problems. We believe that different types of networks are required for each application domains. Our approach therefore is to have a very flexible network design, highly scalable, that allows to easily accommodate the various needs. This paper presents the design of our network on chip, which is part of the platform we are developing for reconfigurable systems. The present design allows us to instantiate arbitrary network topologies, has a low latency and high throughput.

Fast Multi-Dimension Multi-Choice Knapsack Heuristic for MP-SoC Run-Time Management

Since the application complexity is growing and applications can be dynamically activated, the major challenge for heterogeneous multi-processor platforms is to select at run time an energy-efficient mapping of these applications. Taking into account that many different possible implementations per application can be available, and that the selection must meet the application deadlines under the available platform resources, this optimization problem can be modeled as a Multi-dimension Multi-choice Knapsack Problem (MMKP), being NP-hard. Not only algorithms for exact solution, but also state-of-the-art heuristics for real-time systems, are still too slow for run-time management of multi-procesor platforms. This paper provides a new greedy heuristic for finding near-optimal solutions of the MMKP, being fast enough for the considered environment. The main contribution of this heuristic is: (1) the derivation of the Pareto sets from the initial MMKP to reduce the search space, (2) the sorting of all Pareto points together in a single two-dimension search space, where (3) a fast greedy algorithm solves the MMKP. Experiments show that our heuristic finds solutions close to the ones obtained by the fastest state-of-the-art heuristics (within 0% to 0.4% of the solution value), in just a fraction of the execution time (more than 97.5% gain on a StrongARM processor) and can run in less than lms for multi-processor problem sizes

Run-Time Management of a MPSoC Containing FPGA Fabric Tiles

Multimedia applications, like, e.g., 3-D games and video decoders, are typically composed of communicating tasks. Their target embedded computing platforms (e.g., TI OMAP3, IBM Cell) contain multiple heterogeneous processing elements. At application design-time, it is often unknown which applications will execute simultaneously. Hence, resource assignment decisions need to be made by a run-time manager. Run-time assignment of these communicating tasks onto the communication and computation resources of such a multiprocessor platform is a challenging task. In the presence of fine-grain reconfigurable hardware processing elements, the run-time manager also needs to consider the creation of a so-called configuration hierarchy. Instead of executing a dedicated hardware task, the fine-grain reconfigurable hardware fabric hosts a programmable softcore block that, in turn, executes the task functionality. Hence, the next challenge for run-time management is to efficiently handle a configuration hierarchy. This paper details a run-time task assignment heuristic that performs fast and efficient task assignment in a multiprocessor system-on-chip containing fine-grain reconfigurable hardware tiles. In addition, this algorithm is capable of managing a configuration hierarchy. We show that being capable of handling a configuration hierarchy significantly improves the task assignment performance (i.e., success rate and assignment quality). In several cases, adding a configuration hierarchy improves the assignment success rate of the assignment heuristic by 20%.

Run-time support for heterogeneous multitasking on reconfigurable SoCs

In complex reconfigurable systems on chip (SoC), the dynamism of applications requires an efficient management of the platform. To allow run-time management of heterogeneous resources, operating systems (OS) and reconfigurable SoC platforms should be developed together. For run-time support of reconfigurable architectures, the OS must abstract the reconfigurable computing resources and provide an efficient communication layer. This paper presents our efforts to simultaneously develop the run-time support and the communication layer of reconfigurable SoCs. We show that networks-on-chip (NoC) are an ideal communication layer for dynamically reconfigurable SoCs, explain how our OS provides run-time support for dynamic task relocation and detail how hardware parts of the OS are integrated into the higher layers of the NoC. An implementation of the OS and of the dedicated communication layer on our reconfigurable architecture supports the concepts we describe.

Low Cost Task Migration Initiation in a Heterogeneous MP-SoC

Run-time task migration in a heterogeneous multiprocessor system-on-chip (MP-SoC) is a challenge that requires cooperation between the task and the operating system. In task migration, minimization of the overhead during normal task execution (i.e., when not migrating) and the minimization of the migration reaction time are important. We introduce a novel technique that reuses the processors debug registers in order to minimize the overhead during normal execution. This paper explains our task migration proof-of-concept setup and compares it to the state-of-the art. By reusing existing hardware and software functionality our approach reduces the run time overhead.

Fast multidimension multichoice knapsack heuristic for MP-SoC runtime management

Since the application complexity is growing and applications can be dynamically activated, the major challenge for heterogeneous multiprocessor platforms is to select at runtime an energy-efficient mapping of these applications. Taking into account that many different possible implementations per application can be available, and that the selection must meet the application deadlines under the available platform resources, this runtime optimization problem can be modeled as a Multidimension Multichoice Knapsack Problem (MMKP), which is known to be NP-hard. Not only algorithms for an optimal solution, but also state-of-the-art heuristics for real-time systems are still too slow for runtime management of multiprocessor platforms. This article provides a new fast and lightweight heuristic for finding near-optimal solutions for MMKP problems. The main contribution of this heuristic is: (i) the Pareto filtering of each initial MMKP set to reduce the search space, (ii) the sorting of all Pareto points together in a single two-dimension search space, where (iii) a very fast greedy algorithm solves the MMKP. Experiments show that our heuristic finds solutions close (within 0% to 0.4%) to the ones obtained by the fastest state-of-the-art heuristics, in just a fraction of the execution time (more than 97.5% gain on a StrongARM processor) and can run in less than 1ms for multiprocessor problem sizes. This is required for realistic OS reaction times in video and wireless application sets.