Andrei Bartic

Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs

Multimedia support appears on embedded platforms, such as WAP for mobile phones. However, true multimedia applications require both the computation power that only dedicated hardware can provide and the flexibility of software implementations. To this end, we are investigating reconfigurable architectures, composed of an instruction-set processor running software processes and coupled to an FPGA on which hardware tasks are spawned by dynamic partial reconfiguration. This paper focuses on two main aspects. It explains how separating communication from computation enables hardware multi-tasking and it describes our implementation of a fixed communication-layer that decouples the computation elements, allowing them to be dynamically reconfigured. This communication layer is an interconnection network, implemented on a Virtex FPGA, allowing fast synchronous communication between hardware tasks implemented on the same matrix. The network is a 2D torus and uses wormhole routing. It achieves transfer rates up to 77.6 MB/s between two adjacent routers, when clocked at 40 MHz. Interconnection networks on FPGAs allow fine-grain dynamic partial reconfiguration and make hardware multi-tasking a reality.

Preisach model for the simulation of ferroelectric capacitors

The emerging ferroelectric technology needs a reliable model for the simulation of the ferroelectric capacitors. This model would play a crucial role in designing new ferroelectric nonvolatile memories. As a main requirement, such a model must allow the calculation of the polarization variations for an arbitrary voltage applied to the ferroelectric. However, in spite of the large efforts made in modeling, most of the existing solutions fail to satisfy the above requirement or lack a minimal physical background. To address these problems, we developed a model based on a ferroelectric interpretation of the Preisach theory of hysteresis. In this articles, we try to elucidate how this theory, initially developed for ferromagnetic particles, can be adapted to the ferroelectric materials, despite the many differences between the two. Because the Preisach theory assumes a distribution of the coercitive voltages, we try to clarify its physical meaning in the case of the ferroelectric materials and propose a methodology to determine this distribution experimentally. To facilitate the implementation of the model, the experimental results are then fitted by an analytic function and the whole bidimensional distribution is calculated using a linear approximation. To evaluate the validity of the model, we performed simulations using the Spectre® circuit simulator and the results are in very good agreement with the measurements for the saturated hysteresis loops. The differences existing for the partial loops are mainly due to the linear approximation used for the Preisach distribution. This model can be successfully used for the design of the real memories.

Run-time support for heterogeneous multitasking on reconfigurable SoCs

In complex reconfigurable systems on chip (SoC), the dynamism of applications requires an efficient management of the platform. To allow run-time management of heterogeneous resources, operating systems (OS) and reconfigurable SoC platforms should be developed together. For run-time support of reconfigurable architectures, the OS must abstract the reconfigurable computing resources and provide an efficient communication layer. This paper presents our efforts to simultaneously develop the run-time support and the communication layer of reconfigurable SoCs. We show that networks-on-chip (NoC) are an ideal communication layer for dynamically reconfigurable SoCs, explain how our OS provides run-time support for dynamic task relocation and detail how hardware parts of the OS are integrated into the higher layers of the NoC. An implementation of the OS and of the dedicated communication layer on our reconfigurable architecture supports the concepts we describe.

Badminton Playing Robot - a Multidisciplinary Test Case in Mechatronics

Abstract We present a Mechatronics design approach and related technologies for a badminton playing robot, as a first stage of a multi-year project. The robot is using non-modified shuttles and rackets, which are detected and localized using purely visual information. The robot subsystems are presented: mechanical design, visual detection of the shuttle, shuttle trajectory estimation and interception, actuation, control hardware and software. The paper demonstrates the multidisciplinary nature of the Mechatronics.

Hardware and a Tool Chain for ADRES

Until recently, only a compiler and a high-level simulator of the reconfigurable architecture ADRES existed. This paper focuses on the problems that needed to be solved when moving from a software-only view on the architecture to a real hardware implementation, as well as on the verification process of all involved tools.

Constant-current study of dielectric breakdown of Pb(Zr,Ti)O3 ferroelectric film capacitors

Abstract This paper addresses the problem of time-dependent dielectric breakdown of Pb(Zr,Ti)O3 (PZT) thin films. It is shown by using constant-current breakdown measurements, that for PZT film capacitors with Pt and SrRuO3 (SRO) electrodes thebreakdown onset is controlled by charge to breakdown (QBR) rather than the voltage applied to the capacitor. The QBR value for the asymmetrical Pt/SrRuO3/PZT/Pt capacitors is found to be much higher that for the Pt/PZT/Pt system. Polarization fatigue caused by bipolar voltage stress provokes a substantial decreasein charge to breakdown. These results can be interpreted in terms of percolation modelused for breakdown in SiO2, where the QBR is associated with injected-carrier-assisted creation of the critical concentration of defects required for formation of the breakdown paths. The observed variation of the QBR values depending on the electrode material (i) and polarization fatigue (ii) are inteipreted in terms of current redistribution across the area of the capacitor, specifically current redistribution between grains and grain boundaries (case (i)) or current redistribution between fatigued and nonfatigued areas (case(ii)).

Explanation of the non-saturating behavior of the hysteresis loop based on the relaxation current

Abstract The hysteresis loop of ferroelectric thin film capacitors, shows sometimes non-saturation effects, i.e. the high electric field parts of the hysteresis loop do not close and the apparent remanent polarization increases with the amplitude of the measurement signal. Several models attributed this effect to the presence of leakage current, but the very high current levels predicted have not been always confirmed by the direct measurements of the DC leakage. Here, we show that the relaxation current, rather than the true DC leakage current can, in these cases, explains the non-saturating behavior. This effect would than not be caused by the movement of free charges, but rather to of the localized ones.

Effect of crystallisation on fatigue in sol-gel PZT ferroelectric capacitors with reactively sputtered RuO/sub 2/ electrode layers

Two new approaches for improving fatigue performance of sol-gel PZT based ferroelectric capacitors with RuO/sub 2/ electrodes are discussed. First, minimizing the time delay between RuO/sub 2/ sputtering and sol-gel PZT spinning increases the remanent polarisation of the crystallised PZT. Second, the use of thin (/spl sim/5 nm) high-Ti PZT seed layer was found to be effective for improving fatigue performance. For an optimized seedlayer thickness, FECAPs with excellent fatigue characteristics (less than 10% decrease in P/sub r/ after 10/sup 11/ cycles) were obtained.

Implementation of a ferroelectric capacitor model using the Preisach hysteresis theory

Abstract The design of the new ferroelectric memories requires a ferroelectric capacitor model that should be easy to incorporate in a circuit simulator and easy to calibrate based on the experimental measurements. Such a model can be developed by applying the Preisach theory of hysteresis to ferroelectric materials. This theory assumes a distribution of the ferroelectric coercitive voltages. This paper presents the Preisach model and its implementation for the ferroelectric materials based on the experimental determination of the bidimensional Preisach distribution. The relaxation current of the ferroelectric capacitor is also incorporated in the model. Relaxation plays an important roll in the frequency response of these materials. The whole model was implemented into the Spectre® circuit simulator. The simulations of the hysteresis loops show a good agreement with the experiment even for partial hysteresis loops. The memory cell simulations show that the model can be successfully used for the real memory design.

Quantitative determination of the dielectric constant of the interfacial layer in PZT ferroelectric capacitors

The crystallization of PbZr/sub 0.2/Ti/sub 0.8/O/sub 3/ thin films was investigated by varying the crystallization temperature and time. Some of the films were not fully crystallized presenting amorphous top layers. The films have been structurally characterized by XTEM and XRD, and electrically characterized by hysteresis and CV measurements. The evolution of orientation and crystallization is observed for the different conditions and is correlated with hysteresis loops. The dielectric constant is determined for both the amorphous layers and the crystalline phase, and the CV behavior is explained.