Paul Hendrickx

10×10nm 2 Hf/HfO x crossbar resistive RAM with excellent performance, reliability and low-energy operation

We report on worlds smallest HfO2-based Resistive RAM (RRAM) cell to date, featuring a novel Hf/HfOx resistive element stack, with an area of less than 10×10 nm2, fast ns-range on/off switching times at low-voltages and with a switching energy per bit of <0.1pJ. With excellent endurance of more than 5.107cycles, large on/off verified-window (>50), no closure of the on/off window after 30hrs/200C and failure-free device operation after 30hrs/250C thermal stress, the major device-level nonvolatile memory requirements are met. Furthermore, we clarify the impact of film crystallinity on cell operation from a scalability viewpoint, the role of the cap layer and bring insight into the switching mechanisms.

Analytical percolation model for predicting anomalous charge loss in flash memories

Data retention in flash memories is limited by anomalous charge loss. In this work, this phenomenon is modeled with a percolation concept. An analytical model is constructed that relates the charge-loss distribution of moving bits in flash memories with the geometric distribution of oxide traps. The oxide is characterized by a single parameter, the trap density. Combined with a trap-to-trap direct tunneling model, the physical parameters of the electron traps involved in the leakage mechanism are determined. Flash memory failure rate predictions for different oxide qualities, thicknesses and tunnel-oxide voltages are calculated.

Analytical model for failure rate prediction due to anomalous charge loss of flash memories

Anomalous charge loss in flash memories is modeled with a percolation concept. An analytical model is constructed that relates the charge loss distribution of moving bits in flash memories with the geometric distribution of oxide traps, thus linking the phenomenological description of moving bits to physical conduction models. This model allows flash memory failure rate predictions for different oxide qualities and thicknesses.

Statistical model for stress-induced leakage current and pre-breakdown current jumps in ultra-thin oxide layers

We present a statistical, unified picture of Stress-Induced Leakage Current (SILC) generation, pre-breakdown current steps and breakdown in 2.4 nm oxide layers during a constant voltage stress. Pre-breakdown current steps were investigated through gate voltage ramp measurements and modeled by means of a percolation model with variable trap-trap distance. During oxide stress, first single-trap conduction paths are formed, followed by two-trap conduction paths which are identified as pre-breakdown current steps in small devices. Finally, a highly conducting path is formed which triggers breakdown.

Embedded HIMOS(R) flash memory in 0.35 /spl mu/m and 0.25 /spl mu/m CMOS technologies

In this paper, the performance and reliability characteristics of the 0.35 /spl mu/m/0.25 /spl mu/m High Injection MOS (HIMIOS(R)) technology is described in detail. This flash EEPROM technology relies on source-side injection for programming and Fowler-Nordheim tunneling for erasing, and has been successfully implemented in a 1 Mbit memory array embedded in a 0.35 /spl mu/m CMOS technology, adding only about 30% to the processing cost of digital CMOS. Due to its triple gate structure, the HIMOS(R) cell exhibits a high degree of flexibility and scalability. A fast programming operation (10 /spl mu/s) at 3.3 V supply voltage is combined with an endurance of well over 100000 program/erase cycles, immunity to all possible disturb effects and a retention time that largely exceeds 100 years at 125/spl deg/C. Furthermore, the cell has been scaled to a 0.25 /spl mu/m version, which is a laterally scaled version with the same operating voltages and tunnel oxide thickness. The use of secondary impact ionization is investigated as well and proves to be very promising for future generations when the supply voltage is scaled below 2.5 V.

High-drive current (>1MA/cm 2 ) and highly nonlinear (>10 3 ) TiN/amorphous-Silicon/TiN scalable bidirectional selector with excellent reliability and its variability impact on the 1S1R array performance

An optimized TiN/amorphous-Silicon/TiN (MSM) two-terminal bidirectional selector is proposed for high density RRAM arrays. The devices show superior performance with high drive current exceeding 1MA/cm2 and half-bias nonlinearity of 1500. Excellent reliability is fully demonstrated on 40nm-size crossbar structures, with statistical ability to withstand bipolar cycling of over 106 cycles at drive current conditions and thermal stability of device operation exceeding 3hours at 125°C. Furthermore, for the first time, we address the impact of selector variability in a 1S1R memory array, by including circuit simulations in a Monte Carlo loop and point out the importance of selector variability for the low resistive state and its implications on the read margin and power consumption.

Thermal stability of copper Through-Silicon Via barriers during IC processing

Barrier reliability in 3D Through-Si Via (TSV) Cu interconnections requires particular attention as these structures come very close to the active devices and Cu diffusion into the silicon substrate would significantly affect device performance. This work focuses on a via-middle process flow, which implies processing of the 3D-TSV after the front-end-of-line (FEOL) process, but before the back-end-of-line (BEOL) interconnect process. This results in several high temperature processing steps after TSV fabrication, including a final device wafer sintering step, generally in the 400°C range. Thus, it becomes essential to study the stability of the TSV Cu-barrier at these temperatures to ensure a reliable integration of 3D TSV in CMOS wafers. We report on the thermal stability of Ta and Ti barriers and we show that 5nm Ta barriers are thermally stable, while Ti-barriers require thicknesses above 5nm to guarantee their thermal stability.

On the Bipolar Resistive Switching Memory Using TiN/Hf/HfO2/Si MIS Structure

TiN/Hf/HfO 2 /poly-Si structure was employed as the platform to investigate the resistive switching mechanism of metal-insulator-semiconductor (MIS)-based resistive random access memory (RRAM) devices. Based on the presence of a HfSiO x interfacial layer containing a large amount of oxygen vacancy defects, a resistive switching model is proposed to explain the observed bipolar switching behavior which is of opposite operation polarity as compared to metal-insulator-metal (MIM)-based TiN/Hf/HfO 2 /TiN RRAM devices. The dependence of dopant type/concentration on operation voltage is explained by depletion/accumulation effect of poly-Si bottom electrode. In addition, the MIS-based RRAM devices exhibit good reliability performance in terms of stable dc switching endurance up to 100 cycles and ten-year retention ability at 85 ° C, with memory window higher and close to 100, respectively. The results suggest that MIS-based RRAM using Hf/HfO 2 is a promising alternative for next-generation nonvolatile applications.

Failure Rate Prediction and Accelerated Detection of Anomalous Charge Loss in Flash Memories by Using an Analytical Transient Physics-Based Charge Loss Model

We introduce an analytical physics-based model for the transient simulation of anomalous charge loss in flash memories. This model is applied to determine the bit failure rate and the time-to-failure due to anomalous charge loss. This model can also be used to introduce an accelerated method for the detection of bits suffering from anomalous charge loss.

Time Dependent Anomalous Charge Loss Modeling in Flash Memories and an Accelerated Testing Procedure

Data retention is the most critical issue of nonvolatile memories (NVM). Because of the decreasing tunnel oxide thickness, this data retention is determined by a limited population of bits with larger than expected charge loss. This anomalous charge loss has generally been ascribed to the high-field stress during the (tunnel) erase operation. Although several models have been suggested Il-5], up till now there is no commonly accepted charge loss model available. In this paper the direct tunneling model (DT) is proposed to describe the transient behavior of anomalous charge loss, to model accelerated testing by drain disturb, and to derive a simplified analytical method for failure rate prediction.