Jan Van Houdt

A model for tunneling current in multi-layer tunnel dielectrics

Abstract In this paper, we present a model for the tunneling currents through multi-layer stacks based on the independent electron approximation and using an Airy functions based transfer matrix formalism. The transmission coefficient of a tunneling electron is exactly calculated using a simple compact quasi-analytical formula. Comparison with the traditional WKB models reveals differences for particular stack structures. This model is applied to the analysis of multi-layer tunnel dielectrics that aim at replacing the conventional tunnel oxide in non-volatile memory devices. Analysis of the tunneling current for dual-layer stacks shows possibilities for higher speed and/or lower voltage programming, which can be achieved with high- k materials considered for SiO 2 replacement as gate dielectric.

Characterization of charge trapping in SiO2/Al2O3 dielectric stacks by pulsed C–V technique

Abstract In this work, charge trapping in SiO 2 /Al 2 O 3 dielectric stacks is characterized by means of pulsed capacitance–voltage measurements. The proposed technique strongly reduces the measurement time and, as a consequence, the impact of charge trapping on the measurement results. Flat band voltage shift and fast current transient during short stress pulses are systematically monitored and the centroid and the amount of the trapped charge are extracted using a first-order model.

Cross-cell interference variability aware model of fully planar NAND Flash memory including line edge roughness

Abstract The main reliability issue of highly scaled floating gate NAND Flash memories is the cross-cell interference phenomenon. This is an active area of research in microelectronics engineering. In the last decade, there has been much progress and there are already proposed models for extraction of parasitic capacitive couplings within floating gate transistors. However, most of simulation-based methodologies for evaluation of the impact of cross-cell interference on the electrical behavior rely on deterministic capacitive coupling, neglecting the variability effects. This approach ignores the variable nature of the capacitive couplings caused by technological limitations such as line edge roughness (LER) in advanced technological nodes. The aim of this work is to present an alternative approach of modeling threshold voltage disturbance propagation in a raw NAND Flash memory array, sourced by variability-affected parasitic capacitive couplings. The major contribution of this work is the introduction of probabilistic framework to link the process technology and system level.

Applying Complementary Trap Characterization Technique to Crystalline

The operation and reliability of nonvolatile memory concepts based on charge storage in nitride layers, such as TANOS (TaN/Al₂O₃/Si₃N₄/ SiO₂/Si), require detailed information on the energy and spatial distribution of the charge defects in both the nitride and the Al₂O₃ blocking dielectric. This paper focuses on the characterization of Al₂O₃. We have successfully applied complementary trap characterization techniques to crystalline γ-phase- Al₂O₃ in order to obtain a complete picture of the spatial and energetic distribution of the defect density. As a result, two defect types at energy levels 1.8 and 3.5 eV below the conduction band edge are found.

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Flash pitch scaling will lead to cells for which the wordline no longer fits between the floating gates, which results in loss of sidewall coupling, causing unacceptable program saturation due to IPD leakage. We present a dual layer poly/metal floating gate (FG) memory device avoiding this saturation and demonstrate +4V programming above the fresh level in a fully planar cell without sidewall coupling using an Al2O3 IPD. The data retention at 200C and cycling performance up to 100k cycles are similar to cells with poly FG.

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High-k insulators are currently considered for SiO2 replacement as gate dielectrics in sub-100 nm complementary metal-oxide-semiconductor (CMOS) technology nodes. The use of double-layer high-k stacks as tunnel dielectrics could bring important benefits in the nonvolatile memory operation by either reducing the operating voltages and/or increasing the programming speed. In this paper, the influence of the high-k parameters on the tunneling current and requirements for achieving higher programming speed without compromising retention are discussed. We show that enhancement of the tunneling current is possible with two-layer low-k/high-k dielectric stacks and confirm the theoretical results based on our experimental data.

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A new discharge-based multipulse technique has been developed in this paper, which overcomes the shortcomings of the existing techniques, such as the charge pumping, charge injection and sensing, and two-pulse C-V techniques. It captures the energy signature for electron traps across high-κ materials and can be a useful tool for material selection during technology development. Trap distributions in HfO₂, AI₂O₃, and HfAlO have been compared to identify the effects of material variation. It is observed that hafnium gives the shallow traps at about 0.45 eV above the silicon conduction band bottom (Si E_CB), and the deep traps at 0.8 eV below the Si E_CB are caused by aluminum. HfO₂ combines the features in HfO₂ and AI₂O₃. A peak near the Si E_CB has been observed in all the three materials.

for Improved Understanding of Nonvolatile Memory Operation and Reliability

In this work the authors present a thorough investigation of charge retention in memory cells with SiO2/Al2O 3 interpoly dielectric (IPD) stacks, using a fully planar stacked gate memory cell with self-aligned floating gate. This structure is interesting for future area scaling and allows high-k materials and metal gates to be easily introduced. It is shown that the retention behaviour is determined by room temperature charge loss and directly correlated to the properties of the IPD layer. From a comparison between different thicknesses, gate materials and post-deposition anneals (PDA) of the Al2O3 layer, it is also found that the bottom oxide thickness is the key parameter for retention, while the use of a poly gate and a low PDA temperature yield further improvement

Novel dual layer floating gate structure as enabler of fully planar flash memory

We investigate the use of HfO2 based high- k materials as inter-gate dielectric in hybrid floating gate based memory cells for planar NAND flash. The incorporation of Al or Gd in the HfO2 allows reaching higher k values as compared with pure HfO2 through different crystalline characteritics. However, a difficult compromise is to be found between the k value and low leakage due to grain boudaries in a material with large crystalline proportions. Hence, HfGdO reaches a k value as high as 23 but shows important leakage that translates into early program saturation and room temperature charge loss. The HfAlO has more moderate k of ~ 16 but shows lower leakage leading to improved device performances. Finally, a three layer stack where a high-k HfAlO layer is encapsulated into Al2O3 thinner layers shows overall best compromise in terms of program/erase window and retention.

Enhanced Tunneling Current Effect for Nonvolatile Memory Applications

A fast response technique is developed to investigate the short-term postprogram and post-erase discharge in Flash memory devices. The procedure is based on fast VTH-evaluation methods developed for bias temperature instability and provides the transient characteristics after 20 ms under the program or erase conditions. The following different structures are investigated: 1) SiO2/high-k stacks; 2) charge trap memories; 3) and floating gate memories. Dielectrics targeted for Flash memory applications are used as charge trap layers and interpoly di electrics. In this paper, we show results on Al2O3, DyScO, GdScO, and hexagonal and perovskite LuAlO. The postprogram and post-erase curves hold useful information about the dielectric properties and are used as a fast screening technique for alternative materials.