D. Wellekens

CMOS Process-Compatible High-Power Low-Leakage AlGaN/GaN MISHEMT on Silicon

We report on a novel Au-free CMOS process-compatible process for AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors. The process starts from a 150-mm GaN-on-Si substrate with an embedded Si₃N₄/Al₂O₃ bilayer gate dielectric, encapsulated by a high-temperature low-pressure chemical vapor deposited nitride layer. Power devices with a 20-mm gate width reach a maximum output current of 8 A, a breakdown voltage of 750 V, and a specific on-resistance <i>R</i>_{on, sp} of 2.9 mΩ·cm². The off-state drain leakage at 600 V is 7 μA. We show robust gate dielectrics with a large gate bias swing.

SILC-related effects in flash E/sup 2/PROM's-Part I: A quantitative model for steady-state SILC

In this paper a quantitative model for the steady-state component of the stress induced leakage current (SILC) is developed. The established model is based on the observation of basic degradation monitors on conventional, thermal SiO/sub 2/ gate dielectrics in the thickness range of 6.8-7.1 nm. From a systematic, experimental study, it has been found for the first time that the steady-state SILC, observed after a wide range of constant current stress (CCS) conditions (gate injection polarity), can be uniquely described by a simple, semi-empirical relation, which consists of two parts: 1) the dependence on the measurement field is described as Fowler-Nordheim (FN) tunneling through an oxide barrier of reduced but fixed height (i.e., 0.9 eV), and 2) the level of the SILC at a fixed oxide field is given by the density of neutral bulk oxide traps. Except for a calibration, depending on the oxide thickness and processing, no model parameters have to be adjusted in order to describe all our data. Also, based on bake experiments it has been concluded that interface traps are not causally related to the steady-state SILC in spite of the linear relation which exists between both. Furthermore, these bake experiments provide new evidence that bulk oxide traps play a crucial role in the SILC conduction mechanism.

Analytical percolation model for predicting anomalous charge loss in flash memories

Data retention in flash memories is limited by anomalous charge loss. In this work, this phenomenon is modeled with a percolation concept. An analytical model is constructed that relates the charge-loss distribution of moving bits in flash memories with the geometric distribution of oxide traps. The oxide is characterized by a single parameter, the trap density. Combined with a trap-to-trap direct tunneling model, the physical parameters of the electron traps involved in the leakage mechanism are determined. Flash memory failure rate predictions for different oxide qualities, thicknesses and tunnel-oxide voltages are calculated.

HIM0S-a high efficiency flash E/sup 2/PROM cell for embedded memory applications

A flash E/sup 2/PROM device which is programmed with a highly efficient hot-electron injection mechanism is described. This high-injection MOS (HIMOS) device combines a very high programming speed at 5-V-only operation with a low development entry cost, which renders it highly attractive for embedded memory applications. The HIMOS concept exhibits complete soft-write immunity and the possibility of overerasure without causing any problem in a memory architecture. It is shown that this device can also operate with a 3.3-V voltage supply, which is of a major importance for the next generation of submicron flash E/sup 2/PROM technologies. >

Au-Free AlGaN/GaN Power Diode on 8-in Si Substrate With Gated Edge Termination

High-performance AlGaN/GaN diodes are realized on 8-in Si wafers with Au-free CMOS-compatible technology. The diodes are cointegrated on the same substrate together with the AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors and with only one extra lithographic step. The diode anode and the transistor gate are processed together and the same metallization is used for both, avoiding extra metal deposition dedicated to the Schottky junction. A gated edge termination allows obtaining low reverse leakage current (within 1 μA/mm at -600 V), which is several orders of magnitude lower than the one of conventional Schottky diodes processed on the same wafer. Recess is implemented at the anode, resulting in low diode turn-on voltage values.

Au-free CMOS-compatible AlGaN/GaN HEMT processing on 200 mm Si substrates

Au-free CMOS-compatible AlGaN/GaN HEMT devices have been processed on 200 mm Si substrates u sing a typical CMOS tool set. This paper addresses the challenges with respect to the AlGaN/GaN epitaxy, the processing of thick and bowed 200 mm GaN-on-Si wafers, the impact of Ga contamination on the tools, etc.. An enhancement mode AlGaN/GaN MISHEMT process based on barrier recess is used as demonstrator, and yielded fully functional power devices.

Analytical model for failure rate prediction due to anomalous charge loss of flash memories

Anomalous charge loss in flash memories is modeled with a percolation concept. An analytical model is constructed that relates the charge loss distribution of moving bits in flash memories with the geometric distribution of oxide traps, thus linking the phenomenological description of moving bits to physical conduction models. This model allows flash memory failure rate predictions for different oxide qualities and thicknesses.

SILC-related effects in flash E/sup 2/PROM's-Part II: Prediction of steady-state SILC-related disturb characteristics

For Part I see J. de Blauwe et al., vol.45, no.8, pp.1745-50 (1998). In this paper, a new methodology is developed, and applied thereafter, to predict the disturb characteristics of an arbitrary Flash E/sup 2/PROM device which are related to steady-state stress induced leakage current (SILC). This prediction methodology is based on a quantitative model for steady-state SILC, which has been developed on capacitors and nFETs as was reported earlier in Part I. Here, this model is shown to be also valid for tunnel oxide Flash E/sup 2/PROM devices, and used thereafter in a consistent and well-understood cell optimization procedure. The model requires as only input basic cell parameters and an oxide qualification obtained at the capacitor and transistor level.

Fabrication and Performance of Au-Free AlGaN/GaN-on-Silicon Power Devices With

Au-free GaN-based metal-insulator-semiconductor high electron-mobility transistors grown on 150-mm Si substrates are reported. The device characteristics for three different processes are compared: an ohmic-first and a gate-first process with Al₂O₃-only as gate dielectric and a novel approach with a bilayer gate dielectric stack consisting of Si₃N₄ and Al₂O₃. The Si₃N₄ layer was deposited in situ in the metal-organic chemical vapor deposition reactor in the same growth sequence as the rest of the epilayer stack and the Al₂O₃ layer was deposited ex situ by atomic layer deposition. Only the process with the bilayer gate dielectric results in robust devices with a breakdown voltage >600 V. The ohmic contact resistance for Au-free Ti/Al/W metallization scheme is <;1 Ω·mm. The devices show high maximum output current density (>0.4 A/mm); and low gate and drain leakage (<;10^-10 A/mm). The maximum pulsed mode drain-source current of power bars with 20 mm gate width is 8 A. The specific on-state resistance is 2.9 m Ω·cm².

{\rm Al}_{2}{\rm O}_{3}

A new quantitative model is developed that allows an excellent prediction of the disturb behavior of tunnel oxide flash E/sup 2/PROM devices after write/erase cycling and provides a well-understood and consistent cell optimization procedure. This model requires as only input a measurement of the oxide quality on capacitors and transistors, and some basic cell characteristics.