Paul Jayachandran Joseph

A 3D-IC Technology with Integrated Microchannel Cooling

A 3D-IC technology with integrated microchannel cooling is demonstrated in this paper. Fluidic interconnect network fabrication proceeds at the wafer-level, is compatible with CMOS processing and flip-chip assembly and requires four lithography steps. Measurements for single chips prior to 3D stacking reveal that each die in a two chip 3D stack may potentially exhibit a junction-to-ambient thermal resistance of 0.24°C/W. The demonstrated silicon die contain a through-silicon copper via density of 2500/cm2 integrated within the microchannel heat sink.

Wafer-level MEMS packaging via thermally released metal-organic membranes

This paper reports on the design, implementation and characterization of wafer-level packaging technology for a wide range of microelectromechanical system (MEMS) devices. The encapsulation technique is based on thermal decomposition of a sacrificial polymer through a polymer overcoat to form a released thin-film organic membrane with scalable height on top of the active part of the MEMS. Hermiticity and vacuum operation are obtained by thin-film deposition of a metal such as chromium, aluminum or gold. The thickness of the overcoat can be optimized according to the size of the device and differential pressure to package a wide variety of MEMS such as resonators, accelerometers and gyroscopes. The key performance metrics of several batches of packaged devices do not degrade as a result of residues from the sacrificial polymer. A Q factor of 5000 at a resonant frequency of 2.5 MHz for the packaged resonator, and a static sensitivity of 2 pF g −1 for the packaged accelerometer were obtained. Cavities as small as 0.000 15 mm 3 for the resonator and as large as 1 mm 3 for the accelerometer have been made by this method. (Some figures in this article are in colour only in the electronic version)

Wafer-level microfluidic cooling interconnects for GSI

We present a novel CMOS compatible approach to fabricate on-chip microfluidic cooling channels using a spin-on sacrificial polymer material at wafer level. Deep trenches (>100 /spl mu/m) etched into the backside of an IC wafer were successfully filled up by a single spin coating step with a high viscosity sacrificial polymer. A porous overcoat material allows the decomposition of the polymer to form enclosed microchannels. Through chip holes and polymer pipes are used as the inlet/outlet interconnects. Different channel array designs were described and the pressure drop was estimated for a heat flux of 100 W/cm/sup 2/ with DI water flow rate. The resulting cooling scheme offers a simple and compact solution to transfer cooling liquid directly into a GSI chip and is fully compatible with flip-chip packaging.

Wafer-Level Packaging of Micromechanical Resonators

An approach to low-cost, wafer-level packaging of microelectromechanical systems (MEMS), e.g., microresonators, is reported. The process does not require wafer-to-wafer bonding and can be applied to a wide range of MEMS devices. A sacrificial polymer-placeholder is first patterned on top of the MEMS component of interest, followed by overcoating with a low dielectric constant polymer overcoat. The sacrificial polymer decomposes at elevated temperature, and the volatile products from the sacrificial material permeate through the overcoat polymer leaving an embedded air-cavity around the MEMS structure. Thus, the device is released from the sacrificial polymeric material, housed in a protective overcoat. The protected MEMS device can then be handled and packaged like an integrated circuit. The electrical characteristics of the microresonators before and after packaging were essentially the same, showing the packaging scheme does not alter the device performance. This approach is applicable to both surface and bulk micromachined devices

Improved fabrication of micro air-channels by incorporation of a structural barrier

The fabrication of air-channels for microelectromechanical systems and microfluidic devices using polynorbornene and polycarbonates as thermally or photolitically decomposable materials to form air-gaps in dielectric materials has been reported. In this study, the incompatibility of some overcoat polymers with the sacrificial materials was addressed. SiO2 was used as a barrier layer for the fabrication of single- and multi-layer air-channels via different sacrificial and overcoat materials. The structural rigidity of SiO2 mitigates problems associated with overcoat polymers that can easily deform at the processing temperature (overcoat cure or sacrificial decomposition temperature). The chemical inertness and low permeability of SiO2 allows the use of solvent-cast polymers, for which the solvents would have otherwise dissolved the sacrificial material.

A low cost wafer-level MEMS packaging technology

This paper presents a low-cost low-temperature packaging technique for wafer-level encapsulation of MEMS devices fabricated on any arbitrary substrate. The packaging process presented here does not involve wafer bonding and can be applied to a wide variety of MEMS devices after their fabrication sequence is completed. Our technique utilizes thermal decomposition of a sacrificial polymeric material through a polymer overcoat cap, and can be applied to both surface and bulk micromachined structures. Encapsulation of high-g silicon-on-insulator resonators, and thick silicon gyroscopes and accelerometers are presented.

Air-Gap Transmission Lines on Organic Substrates for Low-Loss Interconnects

The fabrication of low-loss transmission line structures with an air dielectric layer is described. The channels are characterized at low frequency (10 and 100 kHz) using capacitance and loss tangent and at high frequency (500 MHz to 10 GHz) using -parameter measurements. The incorporation of an air gap resulted in structures with effective dielectric constants between 1.5-1.8 and significantly lower loss tangents. The fabrication technique could be used to create more complicated air gap transmission line structures for use in monolithic microwave integrated circuits.

Polylithic integration of electrical and optical interconnect technologies for gigascale fiber-to-the-chip communication

Polylithic integration of electrical and optical interconnect technologies is presented as a solution for merging silicon CMOS and compound semiconductor optoelectronics. In contrast to monolithic and hybrid integration technologies, polylithic integration allows for the elimination of optoelectronic and integrated optic device-related processing from silicon CMOS manufacturing. Printed wiring board-level and compound semiconductor chip-level waveguides terminated with volume grating couplers facilitate bidirectional optical communication, where fiber-to-board and board-to-chip optical coupling occurs through a two-grating (or grating-to-grating) coupling path. A 27% increase in the electrical signal I/O projected by and 33% increase in the number of substrate-level electrical signal interconnect layers implied by the International Technology Roadmap for Semiconductors (ITRS) projections for the 32-nm technology generation are required to facilitate 10 Tb/s aggregate bidirectional fiber-to-the-chip communication. Buried air-gap channels provide for the routing of chip or board-level encapsulated air-clad waveguides for minimum crosstalk and maximum interconnect density. Optical signals routed on-board communicate with on-chip volume grating couplers embedded as part of a wafer-level batch package technology exhibiting compatible electrical and optical input/output interconnects. Measurements of grating-to-grating coupling reveal 31% coupling efficiency between two slab, nonoptimized, nonfocusing volume grating couplers.

Characterization of A Polymer-Based MEMS Packaging Technique

This paper presents characterization of a low-cost polymer-based technique for wafer-level packaging of microelectromechanical systems (MEMS). The packaging process does not impose any size limitation to the device and can be applied to a wide variety of MEMS devices regardless of substrate type. Our technique utilizes thermal decomposition of a sacrificial polymer through a polymer overcoat cap, followed by metal deposition to create hermiticity. The method has been applied to surface and bulk micromachined silicon structures including resonators, tunable capacitors and accelerometers. Mechanical and electrical characterization of the packaged devices is reported to be very close to the corresponding values before packaging

Polymer optical interconnect technologies for polylithic gigascale integration

Polymer optical waveguides embedded within buried air-gap cladding regions are presented as part of a wafer-level packaging technology for polylithic integration of optical interconnection with CMOS microelectronics. Functional 5 /spl mu/m wide/25 /spl mu/m pitch optical channels with dielectric/air core/cladding regions exhibit 0.43-1.22 dB/cm. scattering losses for unpassivated and passivated channels. A 1/spl times/4 multimode interference (MMI) power splitter constructed from the same polymer material exhibits 0.23-1.3 dB output power non-uniformity. Volume grating couplers constructed from a second photopolymer material exhibit /spl sim/72% input coupling efficiency.