Todd J. Spencer

A 3D-IC Technology with Integrated Microchannel Cooling

A 3D-IC technology with integrated microchannel cooling is demonstrated in this paper. Fluidic interconnect network fabrication proceeds at the wafer-level, is compatible with CMOS processing and flip-chip assembly and requires four lithography steps. Measurements for single chips prior to 3D stacking reveal that each die in a two chip 3D stack may potentially exhibit a junction-to-ambient thermal resistance of 0.24°C/W. The demonstrated silicon die contain a through-silicon copper via density of 2500/cm2 integrated within the microchannel heat sink.

Wafer-level microfluidic cooling interconnects for GSI

We present a novel CMOS compatible approach to fabricate on-chip microfluidic cooling channels using a spin-on sacrificial polymer material at wafer level. Deep trenches (>100 /spl mu/m) etched into the backside of an IC wafer were successfully filled up by a single spin coating step with a high viscosity sacrificial polymer. A porous overcoat material allows the decomposition of the polymer to form enclosed microchannels. Through chip holes and polymer pipes are used as the inlet/outlet interconnects. Different channel array designs were described and the pressure drop was estimated for a heat flux of 100 W/cm/sup 2/ with DI water flow rate. The resulting cooling scheme offers a simple and compact solution to transfer cooling liquid directly into a GSI chip and is fully compatible with flip-chip packaging.

Air-Gap Transmission Lines on Organic Substrates for Low-Loss Interconnects

The fabrication of low-loss transmission line structures with an air dielectric layer is described. The channels are characterized at low frequency (10 and 100 kHz) using capacitance and loss tangent and at high frequency (500 MHz to 10 GHz) using -parameter measurements. The incorporation of an air gap resulted in structures with effective dielectric constants between 1.5-1.8 and significantly lower loss tangents. The fabrication technique could be used to create more complicated air gap transmission line structures for use in monolithic microwave integrated circuits.

High-Frequency Chip Connections

Advanced interconnects will be required to keep pace with the increasing speed of future microelectronics.

Air cavity low-loss signal lines on bt substrates for high frequency chip-to-chip communication

Chip-to-chip communication across conventional printed circuit boards is limited to low frequencies (a few GHz), thus limiting the aggregate bandwidth without the use of optics. Low-loss, air insulated transmission lines can extend the frequency range of electrical circuitry on fiberglass-epoxy substrates (e.g. FR4 and BT). Described in this paper are electrical signal lines separated only by an airgap fabricated on BT substrates. The structures demonstrated greater than 46 percent reduction in capacitance and greater than 90 percent in loss tangent, which translates to substantially lower losses at high frequencies (10 GHz or greater). Attenuation in these structures have been simulated to be eight times lower than conventional microstrip lines. Air cavity signal lines are currently being integrated on multilayer BT substrates to demonstrate chip-to-chip communication using chips fabricated at the 65-nm node employing cross-talk cancellation techniques.

Air Cavity Transmission Lines for Off-Chip Interconnects Characterized to 40 GHz

In this paper, air cavity transmission lines are integrated into printed circuit boards and packages to enable high-speed low-loss chip-to-chip communication. Microstripline and parallel plate structures with copper conductors separated by an air gap dielectric layer are described. The structures use a sacrificial placeholder material along with conventional microelectronics techniques to create a unique buried copper- air-copper microstripline structure. Transmission lines were characterized by S-parameter measurements to 40 GHz. The capacitance was tracked during fabrication to analyze the impact of the air gap. The effective dielectric constant of the final buried copper-air-copper structure was as low as 1.25.

Air-gap transmission lines for multiprocessor interconnects on FR-4 and BT substrates

The fabrication and characterization of low loss parallel plate and microstrip lines with an air dielectric layer is described. The lines are characterized by capacitance and loss tangent at 10 kHz and 100 kHz and by S-parameters up to 10 GHz. The inclusion of the air-gap significantly reduced the loss tangent and lowered the dielectric constant to between 1.5 and 1.8. More complicated transmission line structures could be fabricated using the described techniques.