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Dive into the research topics where Paul Kwok Keung Ho is active.

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Featured researches published by Paul Kwok Keung Ho.


Multilevel interconnect technology. Conference | 1999

Challenges of damascene etching for copper interconnect

Paul Kwok Keung Ho; Mei-Sheng Zhou; Subhash Gupta; Ramasamy Chockalingam; Jianxun Li; Ming Hui Fan

Dual damascene patterning is essential for the integration of copper into a high performance interconnect, hence the etching process becomes the most important challenge. This paper described the work on the dual damascene etching. The three most common schemes for patterning the dual damascene structure are trench-first, via-first (also known as counter-bore) and self-aligned etchings. Although only self- aligned etching requires the insertion of a stop layer, the stop layer is crucial to all schemes for a better control of the etching uniformity. The impact of using a stop layer with every dual damascene scheme was investigated. Lithography plays an important role in damascene etching. The use of negative-tone photoresist for metal trench masking and the challenge of forming a residue-free damascene structure in the presence of a bottom anti- reflecting coating were discussed.


Process, equipment, and materials control in integrated circuit manufacturing. Conference | 1997

Analysis on the metal etch resist selectivity measurement

Vayalakkara Premachandran; Raymond Joy; Paul Kwok Keung Ho; Lee Wei Lok; Thomas Schuelke; Young Tsai

Absence of a good resist selectivity is a key issue in the metal etch. It becomes increasingly critical when the geometry shrinks below the sub-half micron and the resist thickness reduces further for lithography to get smaller features resolved. Measured values are often quoted based on various techniques like surface profiler or cross section analysis, etc. For a multi step etch recipe we analyzed step by step the etched photoresist cross section for feature sizes between 0.40 . . . 0.65 micrometer and bondpads by using a scanning electron microscope (SEM). We found that the real photoresist margin is independent on the feature size which we explain using a simple geometrical model. However, this value is remarkably smaller than the height of the remaining photoresist on top of the center part of a bondpad measured using a surface profiler. Subsequently, the profiler measurements result in selectivity values which are considerably higher than those measured at small features with cross section SEM analysis. We discuss advantages and limitations of profiler measurements. The comparison between the results of both methods open the possibility to utilize the advantages of surface profiling (e.g. non-destructive approach) by reducing the risk to get overestimated selectivity values for small features. This method is very useful in metal etch process development and forecasting the requirements for the future technology as well as to interpret absolute selectivity often quoted.


Archive | 2001

Method for bonding wafers to produce stacked integrated circuits

Subhash Gupta; Paul Kwok Keung Ho; Sangki Hong


Archive | 1999

Method to create a controllable and reproducible dual copper damascene structure

Paul Kwok Keung Ho; Mei Sheng Zhou; Subhash Gupta


Archive | 1999

Method to avoid copper contamination during copper etching and CMP

Subhash Gupta; Paul Kwok Keung Ho; Mei Sheng Zhou; Ramasamy Chockalingam


Archive | 2000

Method to create a copper diffusion deterrent interface

Simon Chooi; Yakub Aliyu; Mei Sheng Zhou; John Sudijono; Subhash Gupta; Sudipto Ranendra Roy; Paul Kwok Keung Ho; Yi Xu


Archive | 1999

Method to create a copper dual damascene structure with less dishing and erosion

Mei Sheng Zhou; Paul Kwok Keung Ho; Subhash Gupta


Archive | 1998

Chlorine containing plasma etch method with enhanced sidewall passivation and attenuated microloading effect

Mei-Sheng Zhou; Paul Kwok Keung Ho; Thomas Schuelke


Archive | 2000

Method to deposit a copper seed layer for dual damascene interconnects

Paul Kwok Keung Ho; Mei Sheng Zhou; Subhash Gupta; Chockalingam Ramasamy


Archive | 2001

Planarization by selective electro-dissolution

Paul Kwok Keung Ho; Mei Sheng Zhou; Subhash Gupta; Ramasamy Chockalingam

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Subhash Gupta

Chartered Semiconductor Manufacturing

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Mei Sheng Zhou

Chartered Semiconductor Manufacturing

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Simon Chooi

Chartered Semiconductor Manufacturing

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John Sudijono

Chartered Semiconductor Manufacturing

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Sudipto Ranendra Roy

Chartered Semiconductor Manufacturing

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Yakub Aliyu

Chartered Semiconductor Manufacturing

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Yi Xu

Chartered Semiconductor Manufacturing

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Xu Yi

Chartered Semiconductor Manufacturing

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Ramasamy Chockalingam

Chartered Semiconductor Manufacturing

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Mei-Sheng Zhou

Chartered Semiconductor Manufacturing

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