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Dive into the research topics where Simon Chooi is active.

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Featured researches published by Simon Chooi.


Journal of Applied Physics | 2002

Effect of a titanium cap in reducing interfacial oxides in the formation of nickel silicide

W. L. Tan; Kin Leong Pey; Simon Chooi; Jianhui Ye; T. Osipowicz

Interfacial silicon oxide present at the Ni–Si interface hampers the silicidation between Ni and Si. In this work we present findings of the interaction of a Ti cap layer on top of Ni to remove the interfacial native oxide and chemically grown silicon oxide at several annealing temperatures. It was found that at 500 °C, Ti diffuses through the Ni layer and segregates at the Ni/Si interface, which subsequently reduces the interfacial silicon oxide and enables nickel monosilicide (NiSi) formation at 600 °C. The thickness of the Ti cap layer was found to strongly influence the temperature of the onset of nickel silicidation. A thin Ti cap layer resulted in the onset temperature of nickel silicidation being the same as that without a Ti cap layer, whereas a thick Ti cap layer lowered the onset temperature of the nickel silicidation.


Multilevel interconnect technology. Conference | 1998

Post-etching polymer removal in sub-half-micron device technology

Simon Chooi; Zainab Ismail; Ping-Yu Ee; Mei-Sheng Zhou

The accomplishment of low-resistance interconnecting high- density ULSI integrated devices depends on the cleanliness of the via holes before metal deposition. This paper studies the polymer removal of via cleaning after etching and oxygen ashing using hydroxylamine-based organic solvent on an on-axis spray processor. An investigation into the effect of different process parameters such as spray pressure, rotational speed, cleaning duration and cleaning temperature was carried out. While the variation of spray pressure and rotational does not produce significant changes in the via resistance, the variation in the cleaning duration sees a lower via resistance as the duration is decreased. Additionally, the variation in cleaning temperature produces a process window between 75 degrees Celsius and 85 degrees Celsius (inclusive). The bypassing of isopropyl alcohol in the cleaning sequence gives comparable electrical resistance but suffers from high particle counts. There is no significant difference in via resistance for wafers processed on both Semitool Magnum and the wet bench. High resistance of zero and negative enclosed vias is found to be linked to the attack of titanium in the overlying metal stack.


Electrochemical and Solid State Letters | 2002

Impacts of Buffer Oxide Layer in Nitride/Oxide Stack Gate Dielectrics on the Device Performance and Dielectric Reliability

Wenhe Lin; K. L. Pey; Zhong Dong; Victor Seng Keong Lim; Simon Chooi; Mei-Sheng Zhou; Chew-Hoe Ang; Ting-Cheong Ang; W. S. Lau

The device performance and reliability of nitride/oxide stack gate dielectrics with different buffer oxide thickness has been studied. The stack dielectrics were fabricated by in situ H (2%)/O 2 anneal of chemical vapor deposited Si 3 N 4 . Ellipsometry data indicates the formation of SiO 2 at the Si 3 N 4 /Si interface. With decreasing thickness of the buffer oxide, the gate leakage current reduced while the reliability and metal oxide semiconductor field effect transistor performance were degraded. The degradation in the reliability is attributed to the extension of structural strained layer into the Si 3 N 4 bulk. Our results suggest that a buffer oxide of ∼10 A is needed for the implementation of Si 3 N 4 gate dielectric for future high performance complementary metal oxide semiconductor devices.


international interconnect technology conference | 1999

Titanium corrosion in 0.25 /spl mu/m metal interconnects

Leong-Tee Koh; Kho-Liep Chok; He Ming Li; Simon Chooi

This paper studies the effect of post-metal etch wet polymer cleaning on the via resistance of design structures with various enclosures of overlying metal film stacks in prevailing tungsten (W) plugged vias. We observed a new via failure mechanism of enhanced galvanic corrosion of the Ti adhesion layer (anode) immediately overlying the exposed W via (cathode) during the strip process. We solved the high via resistance issue by using an alternative strip chemical which is considered to be an inactive electrolyte for the galvanic reaction between the Ti glue layer sidewall edge and exposed W via.


Multilevel interconnect technology. Conference | 1998

Titanium silicide etching in sub-half-micron device technology

Simon Chooi; Vincent Sih; Soh Yun Siah; Zainab Ismail; Mei-Sheng Zhou

The downscaling in ULSI devices incorporating self-aligned titanium silicide (salicide) has led to the high sheet resistance and junction leakage. Silicon implantation through metal (ITM) and pre-amorphization implantation (PAI) have been investigated to address the concerns. The selective wet chemical stripping of unreacted titanium and/or titanium nitride after salicide formation (salicide etchback) is an important process and is investigated in this paper on an off- axis spray processor. The etching rates of titanium and titanium nitride that were subjected to a rapid thermal annealing (RTA) are about half that of their non-RTA counterparts. The flow rate of the components in SC-1 is found to have the most impact on the etching rates of the titanium nitride and titanium silicide. The variation of the temperature and ratio of ammonium hydroxide, hydrogen peroxide and deionized water in SC-1 produced different etching selectivity of titanium nitride and titanium to silicon dioxide and titanium silicide. The graphical profile of the both salicidation schemes in the active and field regions correlates the distinct slope patterns to the etching of different film materials, and provides a qualitative assessment in the absence of analytical depth profiling. Electrical tests reveal similar gate-to-source drain leakage values for both PAI and ITM salicide schemes using the standard SC-1 cleaning.


Microelectronic Device and Multilevel Interconnection Technology II | 1996

Comparison of spin-on materials in IMD planarization

Simon Chooi; Chew-Hoe Ang; Jia Zhen Zheng; Lap Chan

This paper describes the characterization of an etchback process for the new AlliedSignals Accuspin 418 and Hitachi Chemicals HSG R7-13 low dielectric constant silsesquioxane spin-on polymers and the application to the inter-metal dielectric scheme of a 0.35 micrometers device. A comparison with a conventional polysiloxane spin-on glass (AlliedSignals Accuglass 214) is also briefly discussed. The predominant factor affecting the selectivity of PECVD oxide to spin-on polymer is the CHF3CF4 flow. A low selectivity in which the spin-on polymer etches faster was found to rid of spin-on polymer on top of large metal features where vias may be cut while simultaneously leaving behind sufficient oxide on top of metal lines and the spin-on polymer in the metal spaces. After etchback, a thick PECVD oxide is deposited and planarized by chemical mechanical polishing.


Microelectronic Device and Multilevel Interconnection Technology II | 1996

Process integration of TDEAT-based MOCVD TiN as diffusion barrier for advanced metallization

Fang Hong Gn; Qiong Li; Lap Chan; Simon Chooi

Decreasing contact geometry imposes stringent requirements on barrier metals in providing good barrier against Al-Si interdiffusion. The challenge for the barrier metal technologies is to develop a process to give conformal and thermally stable barrier metal film at low enough temperature, so as to be applicable to multilevel interconnect metallization. Collimated Ti/TiN process results in overhanging at the top of the contact and conformality is no way possible. CVD (Chemical Vapor Deposition) process has been demonstrated to provide excellent conformality and is definitely an attractive option for sub-half micron technology. Process integration of Metalorganic CVD (MOCVD) TiN using TDEAT (Tetrakis(diethylamido) Titanium) precursor and NH3 as co-reactant, together with PVD Ti has been demonstrated as diffusion barrier at contact level for advanced metallization. Two process pressure and temperature regimes of deposition were evaluated. The 30 Torr, 300 degree(s)C higher step coverage process and the 10 Torr, 425 degree(s)C lower resistivity were under study. All barrier stacks went through vacuum break before CVD TiN deposition. RTP was carried out either right after PVD Ti deposition or after CVD TiN deposition. Its impact on contact resistances and junction leakages upon thermal stress were investigated. In addition, the impact of Ti wetting layer on electrical parameters and barrier integrity, which is essential for Al planarization on small geometry contacts, was also studied.


Microelectronic Device and Multilevel Interconnection Technology | 1995

Submicron patterning of AlSiCu/TiN and AlSiCu/TiW films

Simon Chooi; Fang Hong Gn; Lap Chan

As part of our continued studies into improving the performance of multilevel interconnect schemes, we have investigated the film properties and etchability of the AlSiCu/TiN and AlSiCu/TiW film stacks. In this study, two different types of TiN film were deposited by reactive sputtering: low-density (LD) TiN and high-density (HD) TiN. Low-density TiN film was found to have greater oxygen stuffing capability. Both the AlSiCu/TiN and AlSiCu/TiW film stacks can be easily etched anisotropically using high density plasma technology. Barrier integrity of these two film stacks was analyzed by high temperature furnace stress.


Archive | 2001

Non-metallic barrier formations for copper damascene type interconnects

Simon Chooi; Subhash Gupta; Mei-Sheng Zhou; Sangki Hong


Archive | 1999

Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion

Jianxun Li; Simon Chooi; Mei-Sheng Zhou

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Mei Sheng Zhou

Chartered Semiconductor Manufacturing

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Subhash Gupta

Chartered Semiconductor Manufacturing

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Yi Xu

Chartered Semiconductor Manufacturing

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John Sudijono

Chartered Semiconductor Manufacturing

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Paul Kwok Keung Ho

Chartered Semiconductor Manufacturing

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Sudipto Ranendra Roy

Chartered Semiconductor Manufacturing

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Yakub Aliyu

Chartered Semiconductor Manufacturing

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Mei-Sheng Zhou

Chartered Semiconductor Manufacturing

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Lap Chan

Chartered Semiconductor Manufacturing

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Xu Yi

Chartered Semiconductor Manufacturing

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