Paul Muller

A fully integrated 2×2 MIMO dual-band dual- mode direct-conversion CMOS transceiver for WiMAX/WLAN applications

Growing demand in the broadband wireless communication market has resulted in emerging standards such as IEEE 802.16e (mobile WiMAX), which enable high data-rate communication over wide area coverage. Seamless switching between WiMAX and WLAN is envisioned as a means to enable users to stay connected anywhere and anytime. A low-cost low-power small-form-factor dual-mode (802.16e and 802.11b/g/n) dual-band (2.3G to 2.7G and 3.3G to 3.9G) 2×2 MIMO direct-conversion radio in 90nm CMOS has been developed to address this rapidly growing market. The transceiver supports wide dual-frequency bands and multiple signal bandwidths of 3.5, 5, 7, 10, 14, 20, and 40MHz for worldwide dual-mode operations. Many key challenges in WiMAX direct-conversion transceiver design stem from its small subcarrier spacing, which is necessary to combat multipath fading of OFDM signals in 125km/h mobile vehicular environments. With the first subcarrier as close as 7.8125kHz to DC, stringent requirements are imposed on RX and TX flicker noise, TX LO leakage, and LO settling time. Flicker noise in RX is greatly reduced with the adoption of a passive mixer. Several other circuit techniques, system optimizations, and build-in self-calibrations including DC offset with dynamic bandwidth control, IQ mismatch, TX LO leakage, filter bandwidth, LO frequency and amplitude calibrations are used to accomplish high transceiver performance. The chip also achieves excellent WiMAX/WiFi/Bluetooth/GPS/cellular co-existence performance owing to high RX linearity, robust high dynamic range RX AGC with smart blocker detection, and low TX noise. Ultra-wide RX input-signal dynamic range with EVM of better than −35dB to support MIMO 64-QAM OFDM application is achieved. A well-balanced TX gain control scheme is devised to obtain a very wide range of output power with EVM better than −35dB.

Limiting amplifiers for next-generation multi-channel optical I/0 interfaces in SoCs

We present two fully differential limiting amplifiers with and without inductive peaking, designed and integrated in 0.18mum digital CMOS technology. The key design trade-offs, the importance of inductive coupling between neighboring channels, as well as the design of peaking inductors in a standard process are discussed. The amplifiers, which are intended for multichannel integrated optical receiver arrays, achieve a bandwidth of 4GHz and a gain of 32dB. The silicon area occupied by either amplifier is less than 0.5mm2, while the area of the inductors can be further reduced

Silicon resonant-cavity-enhanced photodetector arrays for optical interconnects

High bandwidth short distance communications standards are being developed based on parallel optical interconnect fiber arrays to meet the needs of increasing data rates of inter-chip communication in modern computer architecture. To ensure that this standard becomes an attractive option for computer systems, low cost components must be implemented on both the transmitting and receiving end of the fibers. To meet this low cost requirement silicon based receiver circuits are the most viable option, however, manufacturing high speed, high efficiency silicon photodetectors presents a technical challenge. Resonant cavity enhanced (RCE) Si photodetectors have been shown to provide the required bandwidth-efficiency product and we have recently developed a method to reproduce them through commercially available fabrication techniques. In this work, commercially reproducible silicon wafers with a 90% reflectance buried distributed Bragg reflector (DBR) are used to create Si-RCE photodetector arrays for optical interconnects. The Si-RCE photodetectors have 40% quantum efficiency at 860 nm, a FWHM of 25 ps, and a 3dB bandwidth in excess of 10 GHz. We also demonstrate Si-RCE 12×1 photodetector arrays that have been fabricated and packaged with silicon based amplifiers to demonstrate the feasibility of a low cost monolithic silicon photoreceiver array.

Transimpedance Amplifier Design

The photocurrent generated by the photodetector through optoelectronic conversion of the incoming light must be conditioned to comply with the requirements of the clock and data recovery block. The CDR performs retiming and synchronization of the received data stream, but requires the input signal amplitude to be constant and larger than its input sensitivity. For this purpose, the photocurrent is converted to the voltage domain in the transimpedance amplifier (TIA). This current-voltage (I-V) conversion intrinsically provides signal amplification by the gain Z TIA , commonly called transimpedance gain. Additional gain is then implemented in the limiting amplifier (LA) in the next step of the conditioning process.

Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs

This paper presents an approach to analyzing and modeling of gated-oscillator (GO) -based CDRs and predicting their performance aspects such as jitter tolerance (JTOL) and frequency tolerance (FTOL). It is shown that high JTOL of this topology in addition to their acceptable FTOL and flexible topology, have made them very suitable for short-haul multi-rate applications

Integrated Photonic Systems

Historically, fiber optic communications have experienced an impressive growth in the long-haul domain due to their inherently large bandwidth and low attenuation and dispersion. Indeed, these characteristics allow for the transmission of a large amount of data over long distances at limited latency,which makes optical fibers the medium of choice for intercontinental communication links.

Limiting Amplifier Design

Following the photocurrent-to-voltage conversion performed by the transimpedance amplifier, the limiting amplifier provides additional voltage gain for the signal to satisfy the input sensitivity of the attached clock and data recovery circuit. The amplitude of the CDR input signal must not only exceed this value, the rise and fall times shall also allow for accurate detection of the zero crossings. Due to the signal amplification already operated in the TIA, noise may be less critical in the limiting amplifier, although this argument loses strength in advanced CMOS receivers operating at multi-gigabit data rates, where the achievable TIA gain tends to drop below the kiloohm barrier.

Clock and Data Recovery Circuit

At the output of the limiting amplifier, the amplified data signal with sharpened data edges is available for further processing, but unique interpretation of the received signal requires timing information. Serial communication links do not provide a synchronization signal on a separate channel and therefore the receiver must rely on the extraction of the timing information from the data stream. This clock and data recovery process can be performed in a similar manner in optical communication, electrical serial links, hard drive read-out channels, as well as in some memory interfaces. In the latter field, advocates and opponents of the clock forwarding scheme still debate about the advantages and drawbacks of per-channel clock recovery circuits.

System-Level Specifications

After this general introduction on short-distance fiber-optic communication systems, let us now focus on the receiver design. The receiver can be decomposed into several building blocks discussed below, which today are frequently integrated on separate dies (Figure 4.1). Commercial photodetectors are manufactured using III-V semiconductors like GaAs, InGaAs or InP. The transimpedance amplifiers, as well as the limiting amplifiers, use silicon or silicon–germanium (SiGe) bipolar processes to achieve a high bandwidth-power product. As clock recovery does not require the same gain-bandwidth product and is commonly built with logic gates, it is fabricated in standard CMOS. This technology based breakup remains more or less valid for the limited amount of currently available multichannel receiver solutions [27, 2].

Design and Integration of All-Silicon Fiber-Optic Receivers for Multi-Gigabit Chip-to-Chip Links

This paper presents a top-down approach to the design of all-silicon CMOS-based fully integrated optical receivers. From the system-level requirements, we determine the optimum block-level specifications, based on which the individual building blocks are designed. Measurement results of the manufactured design show operation at data rates exceeding 2.5-Gbps/channel for the detector, the amplification and the clock and data recovery circuits. This proof of concept is the first step towards design optimized, completely integrated, multi-channel optical receivers for high-bandwidth short-distance chip-to-chip interconnects