Paul Peronnard

Real-Life SEU Experiments on 90 nm SRAMs in Atmospheric Environment: Measures Versus Predictions Done by Means of

An experimental platform including 1 Gigabit memory built from 90 nm SRAMs was used for SEU detection during commercial flights. Numbers and natures of observed errors were in good agreement with estimations done using the MUSCA SEP3 platform.

{\rm MUSCA~SEP}^{3}

An approach to reproduce radiation ground testing results for the study of microprocessors vulnerability to single event upset (SEU) is described in this paper. Resulting cross-sections fit very well with measured ones.

Platform

An approach combining the SRAM-based field-programmable gate array static cross-section with the results of fault injection campaigns allows predicting the error rate of any implemented application. Experimental results issued from heavy ion tests are compared with predictions to validate the proposed methodology.

Single-event-upset-like fault injection: a comprehensive framework

This paper presents experimental results putting in evidence the potential weaknesses of a state-of-the-art fault tolerance strategy, the Triple Modular Redundancy (TMR), when implemented in SRAM-based FPGAs. HW/SW fault injection campaigns and accelerated radiation ground tests were performed to quantify the number of faults, Single Event Upsets (SEUs) required to obtain such critical failures.

Combining Results of Accelerated Radiation Tests and Fault Injections to Predict the Error Rate of an Application Implemented in SRAM-Based FPGAs

Integrated circuits (analog, digital or mixed) sensitivity evaluation to Single Event Effects (SEE) requires specific methodologies and dedicated tools. Indeed, such evaluation is based on data gathered from on-line tests performed in a suitable facility (cyclotron, linear accelerator, laser , etc.). The target circuit is exposed to particles fluxes having features (energy and range in Silicon) somewhat representative of the ones the circuit will encounter in its final environment. This chapter will describe and illustrate with experimental results, the methodologies and the hardware and software developments required for the evaluation of the sensitivity to SEE of integrated circuits. Those techniques will be applied to a SRAM-based FPGA and to a complex processor. In case of sequential circuits such as processors, the sensitivity to SEE will strongly depend on the executed program. Hardware/software fault-injection experiments, performed either on the circuit or on an available model, are proved as being complementary of radiation ground testing. Indeed, data issued from fault injection combined with data issued from radiation ground testing allow in accurately predicting the error rate of any program.

Reliability Limits of TMR Implemented in a SRAM-based FPGA: Heavy Ion Measures vs. Fault Injection Predictions

This paper presents principles and results of dynamic testing of an SRAM-based FPGA using time- resolved fault injection with a pulsed laser. The synchronization setup and experimental procedure are detailed. Fault injection results obtained with a DES crypto-core application implemented on a Xilinx Virtex II are discussed.

Integrated Circuit Qualification for Space and Ground-Level Applications: Accelerated Tests and Error-Rate Predictions

This paper presents experimental results putting in evidence the weaknesses of TMR strategy implemented in SRAM-based FPGAs. Results obtained from radiation ground testing are confronted to fault injection campaigns.

Dynamic Testing of an SRAM-Based FPGA by Time-Resolved Laser Fault Injection

The general principle of MUlti- SCAles Single Event Phenomena Predictive Platform (MUSCA SEP3) consists in sequentially modeling all these various physical mechanisms likely to lead to a SEE occurrence in integrated circuits. MUSCA SEP3 inputs include a device description, i.e., the semiconductor active zones, the passivation metallization layers and the package. When the tested circuit is a SRAM, the elementary cell (layout) is described and so the rules of translation allowing modeling the whole memory plan.

Reliability limits of TMR implemented in a SRAM-based FPGA: Heavy ion measures vs. fault injection predictions

This-paper characterizes the effectiveness of an error detection technique that addresses transient faults induced by the environment (radiation, EMC) in processor-based architectures. Experimental results obtained from fault injection sessions performed on two platforms built around a 32-bit digital signal processor and an 8-bit microcontroller, provide objective figures about the efficiency of the proposed approach.