Paul T. M. van Zeijl

Wireless wire-the 60 GHz ultra-low power radio system

This article presents basic issues regarding design and development of a 60 GHz ultra-low power radio system for Ambient Intelligence (AmI) applications. It demonstrates the validity of choosing the 60 GHz frequency band to design low power radios by a mathematical model, and proposes an overview of a cross-layer optimization flow to minimize power dissipation. Moreover, a completed RF front-end architecture, i.e. the transmitter and the receiver, is simulated according to the proposed methodology. Crucial concerns, challenges and solutions are discussed based on it. Simulation results are given, which verify the theoretical conclusions of 120 pJ/bit power consumption.

A low-power, high-sensitivity injection-locked oscillator for 60 GHz WPAN applications

This article presents a 60 GHz low-power injection-locked oscillator in TSMC 65 nm technology. By using the frequency sweeping technique, a simulated 7 GHz total locking range is achieved, which covers the entire 60 GHz ISM band. The simulated settling time is less than 2 ns for each sweeping step with −60 dBm injection power. The DC power consumption is 1 mW of the oscillator core, and 5 mW in total for the input and output buffers, which are mainly used for the matching purpose.

A 70 GHz 10.2 mW self-demodulator for OOK modulation in 65-nm CMOS technology

A 70.86 to 79.29 GHz low-power self-demodulator for on-off-keying (OOK) modulation is realized in TSMC 65-nm CMOS technology. By using a frequency-sweeping injection-locked oscillator (IJLO), the OOK modulated 70 GHz signal is demodulated by itself in a passive mixer and an 8.43 GHz bandwidth is achieved at 10.2 mW power consumption from a 1-V supply. The conversion gain is 10 dB and constant over the entire bandwidth. The core area of the chip is 0.072 mm2.

A 60 GHz ultra low-power wake-up radio

This work presents an ultra low-power duty-cycled wake-up radio system for high-data-rate, short-range millimeter-wave WPAN applications. The asynchronous duty-cycled wake-up power management method is proposed and optimized to reduce the average power consumption. As the design example, a 60 GHz radio system is discussed, which consists of a 4-path phase-array transceiver, a duty-cycled wake-up receiver and the digital control circuits. Theoretical analyses of the optimum duty-cycle factor towards minimum average power are shown accordingly. Simulation results are given and a 230 µW average power consumption is achieved for the entire radio, which leads to about 4000-hour operation time for a 1.5-V 1000-mAh re-chargeable battery.

An EFOM for cross-layer optimization towards low-power and high-performance wireless networks

This paper presents an Equivalent-Figure-of-Merit (EFOM) for designing and evaluating a wireless system towards low power and high performance. Relevant factors like delay, minimum latency, overhead length of a package, package length, data rate, bit-error-rate (BER), pre-receiving time of the receiver, average duty cycle and electronics performance factor are synthesized within a unique model. Comparing to other FOMs like energy per bit Ebit, this EFOM is able to rank the overall performance of a wireless network concerning the information not only power efficiency but also about communication quality (speed, BER, wake-up time, etc.), communication effectiveness and users satisfaction. Applying this model to the system design, a 60 GHz self-demodulating receiver is designed and optimized, which obtains high-speed versatile performance in a low-traffic wireless network with better power efficiency comparing to other low-power wireless interface, e.g. Bluetooth and so on.

Sigma-Delta ADC Clock Jitter in Digitally Implemented Receiver Architectures.

The analog-to-digital (AD) converter in modern multi-band multi-mode software defined radios plays a very important role. This paper will show how the specifications for the clock of a sigma-delta AD-converters can be derived. In contrast to literature, where clock jitter (in psrms) is specified, a different approach will be taken, in which the frequency dependent spurious of the clock signal can be calculated in the case of a GSM receiver

A 73 to 83 GHz, 9-mW injection-locked oscillator in 65-nm CMOS technology

A 73 to 83 GHz injection-locked oscillator (IJLO) is realized in TSMC 65-nm CMOS technology. By using the frequency-sweeping method, a 10 GHz total locking range is achieved with −35 dBm injection power. The power consumption is 9 mW from a 1-V supply. Additional 4 mW and 6 mW are consumed for the input and output buffers respectively for the measurement purpose. The measured sensitivity of the IJLO is −60 dBm. The output power measured at the 50-Ohm load is higher than −10 dBm, and the simulated total settling time of the IJLO is less than 10 µs. The effective core area of the chip is 0.055 mm2.

The theoretical efficiency in digital envelope power amplifiers for WLAN OFDM polar transmitters

Recently a number of polar transmitters for the multi-mode transmission of Wireless-Local-Area-Network (WLAN) and Bluetooth signals have been proposed. These polar transmitters use envelope modulators based on digital-to-analog converters (DACs) as power amplifiers. Such an approach is very useful when the maximum theoretical efficiency of the power-amplifier digital-to-analog converter (PA-DAC) is comparable or better than state-of-the-art architectures. This architecture has the advantage that the phase-modulated input signal can drive the circuit in class-A or class-B, without causing any distortion in the overall signal path. Only at the combination point of the phase-modulated signal and the envelope modulated signal, the distortion in the combined signal becomes important. Here, a calculation of the efficiency for such a PA-DAC is performed for both class-A and class-B using WLAN Orthogonal-Frequency-Division-Multiplex (OFDM) signals. When driving the phase-modulated input of the envelope PA-DAC in class-A, an efficiency of 28% can be reached for a peak-to-average-power-ratio (PAR) of 6 dB, while 20% can be reached for a PAR of 9 dB. Similarly, when driving the phase-modulated input of the PA-DAC in class-B, an efficiency of 44% can be reached for a PAR of 6 dB, while 31% can be reached for a PAR of 9 dB.