Paweł Gryboś

Study of spatial resolution and efficiency of silicon strip detectors with different readout schemes

Abstract The spatial resolution and efficiency of silicon strip detectors with different readout schemes considered for the ATLAS silicon tracker have been studied. A series of simulation tools has been developed for accurate modelling of the detectors and front-end electronics. All important effects like the influence of magnetic field on the charge collection in the detectors, ballistic deficit in the electronics, distributed structure of silicon strips, electronic crosstalk via the interstrip capacitance, noise injection from adjacent channels, effect of the charge collection time on timing performance of silicon strips and radiation damages to detectors and electronics have been taken into account. Two types of front-end electronics, bipolar and CMOS, and three readout schemes, analogue readout of every strip, analogue readout using capacitive charge division and binary readout, have been analysed. The spatial resolution and the efficiency have been studied for particle impact angles between − 10° and + 10°, for p-side and n-side strips separately. In the Monte Carlo analysis the Landau distribution and the electronic noise were taken into account. The effects of the electronic noise on the amplitude as well as on the time measurement were implemented in the analysis.

TOT01, a time-over-threshold based readout chip in 180nm CMOS technology for silicon strip detectors

This work is focused on the development of the TOT01 prototype front-end ASIC for the readout of long silicon strip detectors in the STS (Silicon Tracking System) of the CBM experiment at FAIR - GSI. The deposited charge measurement is based on the Time-over-Threshold method which allows integration of a low-power ADC into each channel. The TOT01 chip comprises 30 identical channels and 1 test channel which is supplied with additional test pads. The major blocks of each channel are the CSA (charge sensitive amplifier) with two switchable constant-current discharge circuits and additional test features. The architecture of the CSA core is based on the folded cascode. The input p-channel MOSFET device, biased at a drain current 500 μA, was optimized for 30 pF detector capacitance while keeping in mind the area constraints — W/L = 1800 μm / 0.180 μm. The main advantage of this solution is high gain (GBW = 1.2 GHz) and low power consumption at the same time. The amplifier is followed by the discriminator circuit. The discriminator allows for a global (multi-channel) differential threshold setting and independent compensation for the CSA output DC-level deviations in each channel by means of a 6-bit digital to analog converter (DAC). The output pulse of this processing chain is fed through a 31:1 multiplexer structure to the output of the chip for further processing. The TOT01 chip has been fabricated in the UMC 0.18 μm CMOS process (Europractice mini@sic). It has 78 pads, measures approximately 1.5x3.2 mm2 and dissipates 33 mW. The channels have 50 μm pitch and each consumes 1.05 mW of power. The chip has been successfully tested. Charge sensitivity parameters, noise performance and first X-ray acquisitions are presented.

Comparison of the charge sharing effect in two hybrid pixel detectors of different thickness

Advances in semiconductor technologies, enable the design of hybrid pixel detectors with ever smaller pixel sizes while maintaining good performance of analogue circuits. Along with the decrease in the size of pixels new, previously unaddressed phenomena are beginning to play an important role. One such phenomenon is the charge sharing effect, where the charge generated by a particle in the vicinity of the pixels border is collected by two or more different detector electrodes and processed in part by two or more independent pixels. In systems operating in the single photon counting (SPC) mode which compares the amplitude of the recorded signal with a predetermined threshold, this may reduce or increase the number of photons counted. In systems which measure the amplitude of the signal recorded, this phenomenon can lead to incorrect results of the amplitude measurements. In order to investigate the effect of charge sharing, measurements were conducted using silicon pixel detectors with the thickness of 300 μ m and 1 mm, 100 μ m × 100 μ m pixel size, connected to the PXD18k ASIC. The pixel array was scanned with 16 keV narrow pencil beam. The measurement setup and the results of the measurements are presented in the article.

Single software platform used for high speed data transfer implementation in a 65k pixel camera working in single photon counting mode

Integrated circuits designed for specific applications generally use non-standard communication methods. Hybrid pixel detector readout electronics produces a huge amount of data as a result of number of frames per seconds. The data needs to be transmitted to a higher level system without limiting the ASICs capabilities. Nowadays, the Camera Link interface is still one of the fastest communication methods, allowing transmission speeds up to 800 MB/s. In order to communicate between a higher level system and the ASIC with a dedicated protocol, an FPGA with dedicated code is required. The configuration data is received from the PC and written to the ASIC. At the same time, the same FPGA should be able to transmit the data from the ASIC to the PC at the very high speed. The camera should be an embedded system enabling autonomous operation and self-monitoring. In the presented solution, at least three different hardware platforms are used—FPGA, microprocessor with real-time operating system and the PC with end-user software. We present the use of a single software platform for high speed data transfer from 65k pixel camera to the personal computer.

Testing multistage gain and offset trimming in a single photon counting IC with a charge sharing elimination algorithm

Designing a hybrid pixel detector readout electronics operating in a single photon counting mode is a very challenging process, where many main parameters are optimized in parallel (e.g. gain, noise, and threshold dispersion). Additional requirements for a smaller pixel size with extended functionality push designers to use new deep sub-micron technologies. Minimizing the channel size is possible, however, with a decreased pixel size, the charge sharing effect becomes a more important issue. To overcome this problem, we designed an integrated circuit prototype produced in CMOS 40 nm technology, which has an extended functionality of a single pixel. A C8P1 algorithm for the charge sharing effect compensation was implemented. In the algorithms first stage the charge is rebuilt in a signal rebuilt hub fed by the CSA (charge sensitive amplifier) outputs from four neighbouring pixels. Then, the pixel with the biggest amount of charge is chosen, after a comparison with all the adjacent ones. In order to process the data in such a complicated way, a certain architecture of a single channel was proposed, which allows for: ⋅ processing the signal with the possibility of total charge reconstruction (by connecting with the adjacent pixels), ⋅ a comparison of certain pixel amplitude to its 8 neighbours, ⋅ the extended testability of each block inside the channel to measure CSA gain dispersion, shaper gain dispersion, threshold dispersion (including the simultaneous generation of different pulse amplitudes from different pixels), ⋅ trimming all the necessary blocks for proper operation. We present a solution for multistage gain and offset trimming implemented in the IC prototype. It allows for minimization of the total charge extraction errors, minimization of threshold dispersion in the pixel matrix and minimization of errors of comparison of certain pixel pulse amplitudes with all its neighbours. The detailed architecture of a single channel is presented together with experimental results and an algorithm for proper gain and offset trimming for better uniformity of the pixel matrix.

Trimming the threshold dispersion below 10 e-rms in a large area readout IC working in a single photon counting mode

We present a new method of an in-pixel threshold dispersion correction implemented in a prototype readout integrated circuit (IC) operating in a single photon counting mode. The new threshold correction method was implemented in a readout IC of area 9.6× 14.9 mm2 containing 23552 square pixels with the pitch of 75 μm designed and fabricated in CMOS 130 nm technology. Each pixel of the IC consists of a charge sensitive amplifier, a shaper, two discriminators, two 14-bit counters and a low-area trim DACs for threshold correction. The user can either control the range of the trim DAC globally for all the pixels in the integrated circuit or modify the trim DACs characteristics locally in each pixel independently. Using a simulation tool based on the Monte-Carlo methods, we estimated how much we could improve the offset trimming by increasing the number of bits in the trim DACs or implementing additional bits in a pixel to modify the characteristics of the trim DACs. The measurements of our IC prototype show that it is possible to reduce the effective threshold dispersion in large-area single-photon counting chips below 10 electrons rms.

Prototype readout electronics and silicon strip detector study for the silicon tracking system at compressed baryonic matter experiment

This paper presents the prototype detector readout electronics for the STS (Silicon Tracking System) at CBM (Compressed Baryonic Matter) experiment at FAIR, GSI (Helmholtzzentrum fuer Schwerionenforschung GmbH) in Germany. The emphasis has been put on the strip detector readout chip and its interconnectivity with detector. Paper discusses the impact of the silicon strip detector and interconnection cable construction on the overall noise of the system and architecture of the TOT02 readout ASIC. The idea and problems of the double-sided silicon detector usage are also presented.

Multichannel Low Noise, Low Power Analogue Readout Chip for Silicon Strip Detectors

A prototype 16-channel readout chip for a X-ray detection system using silicon strip detectors is presented. The chip has been designed as a full custom ASIC for the AMS 1.2 μm CMOS process. Single channel of the circuit consists of low noise, medium speed preamplifier, followed by a shaper and a discriminator. Such a system allows to use silicon strip detectors in the single photon counting mode. Key design issues and optimization of critical design parameters are discussed. Measurement results from the successfully manufactured prototype are presented and discussed.