Krzysztof Kasinski

Time and energy measuring front-end electronics for long silicon strip detectors readout

We report on the design of a self-triggered analog front-end readout electronics dedicated for signal detection from double-sided silicon microstrip sensors with capacitance at the order of tens pF (CDET ≈ 30 pF). The main requirements are: processing input pulses with the average rate of 150 kHz/channel, low power consumption and low noise at the same time. The single channel is built of two different parallel processing chains: the fast and slow. The fast path includes: a fast CR-RC shaper with the peaking time tp = 40 ns, a discriminator, a pulse stretcher and a time stamp latch. It is optimized to determine an input charge arrival time with resolution at the order of few ns. The slow path consists of: a slow shaper with the peaking time tp = 80 ns, a 5-bit flash ADC and a digital peak detector. This chain is dedicated for accurate energy measurement and it is optimized for low noise level. To protect against false noise-related hits coming from noisy fast processing path when the discrimination threshold is set low, the time-stamp validation circuit is used. Two prototype ASICs were implemented in UMC 180 nm CMOS technology: 8-channel AFE-XYTER and 128-channel STS-XYTER.

Back-end and interface implementation of the STS-XYTER2 prototype ASIC for the CBM experiment

Each front-end readout ASIC for the High-Energy Physics experiments requires robust and effective hit data streaming and control mechanism. A new STS-XYTER2 full-size prototype chip for the Silicon Tracking System and Muon Chamber detectors in the Compressed Baryonic Matter experiment at Facility for Antiproton and Ion Research (FAIR, Germany) is a 128-channel time and amplitude measuring solution for silicon microstrip and gas detectors. It operates at 250 kHit/s/channel hit rate, each hit producing 27 bits of information (5-bit amplitude, 14-bit timestamp, position and diagnostics data). The chip back-end implements fast front-end channel read-out, timestamp-wise hit sorting, and data streaming via a scalable interface implementing the dedicated protocol (STS-HCTSP) for chip control and hit transfer with data bandwidth from 9.7 MHit/s up to 47 MHit/s. It also includes multiple options for link diagnostics, failure detection, and throttling features. The back-end is designed to operate with the data acquisition architecture based on the CERN GBTx transceivers. This paper presents the details of the back-end and interface design and its implementation in the UMC 180 nm CMOS process.

STS-XYTER, a high count-rate self-triggering silicon strip detector readout IC for high resolution time and energy measurements

We report on the design of a 128-channel ASIC named STS-XYTER (Silicon Tracking System - X - Y - Time -Energy Read-out) dedicated for signal detection from doublesided silicon microstrip sensors with high capacitance (CDET ≈ 30 pF). The STS-XYTER contains: 128 charge processing channels, a calibration unit, a biasing circuitry based on built-in band-gap reference source and a full digital back-end, which provides synchronization, control and sparsified fast data readout through four, 250 MHz DDR LVDS links based on the CBMnet protocol. The single readout channel uses two parallel signal processing paths (fast and slow) to handle an average rate of input pulses equals 150 kHz and provide an information about both interaction time and deposited charge with good noise performance and low power consumption (6.2 mW/channel) at the same time. The fast path, which is dedicated for determining the input charge arrival time, is built of: a fast shaper, a discriminator, a pulse stretcher and a time stamp latch. The slow path, which is optimized for a particle energy measurement, consists of a slow shaper, a 5-bit flash ADC and a digital peak detector.

TOT02, a time-over-threshold based readout chip in 180 nm CMOS process for long silicon strip detectors

We report on the design and measurements of multichannel ASIC named TOT02, dedicated for the readout of silicon long strip detectors of the Silicon Tracking System (STS) in the CBM experiment at FAIR, GSI. This Integrated Circuit adapts the time-over-threshold (ToT) method for detectors with large capacitance (30pF). The prototype chip has 16 channels comprising of a charge sensitive amplifier with a constant current discharge and a discriminator with 6-bit trimming DAC and it is supplied with digital back-end. The paper presents details of architecture, ENC estimation methodology for ToT systems and test setup together with measurement and simulation results.

TOT01, a time-over-threshold based readout chip in 180nm CMOS technology for silicon strip detectors

This work is focused on the development of the TOT01 prototype front-end ASIC for the readout of long silicon strip detectors in the STS (Silicon Tracking System) of the CBM experiment at FAIR - GSI. The deposited charge measurement is based on the Time-over-Threshold method which allows integration of a low-power ADC into each channel. The TOT01 chip comprises 30 identical channels and 1 test channel which is supplied with additional test pads. The major blocks of each channel are the CSA (charge sensitive amplifier) with two switchable constant-current discharge circuits and additional test features. The architecture of the CSA core is based on the folded cascode. The input p-channel MOSFET device, biased at a drain current 500 μA, was optimized for 30 pF detector capacitance while keeping in mind the area constraints — W/L = 1800 μm / 0.180 μm. The main advantage of this solution is high gain (GBW = 1.2 GHz) and low power consumption at the same time. The amplifier is followed by the discriminator circuit. The discriminator allows for a global (multi-channel) differential threshold setting and independent compensation for the CSA output DC-level deviations in each channel by means of a 6-bit digital to analog converter (DAC). The output pulse of this processing chain is fed through a 31:1 multiplexer structure to the output of the chip for further processing. The TOT01 chip has been fabricated in the UMC 0.18 μm CMOS process (Europractice mini@sic). It has 78 pads, measures approximately 1.5x3.2 mm2 and dissipates 33 mW. The channels have 50 μm pitch and each consumes 1.05 mW of power. The chip has been successfully tested. Charge sensitivity parameters, noise performance and first X-ray acquisitions are presented.

GBT based readout in the CBM experiment

The CBM experiment at FAIR will use GBTX and Versatile Link based readout systems for several of its subdetectors. The paper describes the GBT based readout concept in CBM, emphasizing the common features among systems. Particular choices and features of the readout are motivated mainly by the requirements in the readout of the silicon tracking system (STS). Common developments like a common CBM readout board are presented. The prototype board provides full GBT functionality for all systems, can be interfaced to various prototype readout chains and be refined for later detector specific versions.

Design of versatile ASIC and protocol tester for CBM readout system

Silicon Tracking System (STS), Muon Chamber (MUCH) and Transition Radiation Detector (TRD) subdetectors in the Compressed Baryonic Matter (CBM) detector system at Facility for Antiproton and Ion Research (FAIR) use the same innovative protocol ensuring reliable synchronization of the communication link between the controller and the front-end ASIC, transmission of time-deterministic commands to the ASIC and efficient readout of data. The paper describes the FPGA-based tester platform which can be used both for the verification of the protocol implementation in a front-end ASIC at the design stage, and for testing of the produced ASICs. Due to its modularity, the platform can be easily adapted for different integrated circuits and readout systems.

System-level considerations for the front-end readout ASIC in the CBM experiment from the power supply perspective

New fixed target experiments using high intensity beams with energy up to 10 AGeV from the SIS100 synchrotron presently being constructed at FAIR/GSI are under preparation. Most of the readout electronics and power supplies are expected to be exposed to a very high flux of nuclear reaction products and have to be radiation tolerant up to 3 MRad (TID) and sustain up to 1014/cm2 of 1 MeV neutron equivalent in their life time. Moreover, the mostly minimum ionising particles under investigation leave very little signal in the sensors. Therefore very low noise level amplitude measurements are required by the front-end electronics for effective tracking. Sensor and interconnecting micro-cable capacitance and series resistance in conjunction with intrinsic noise of the charge sensitive amplifier are dominant noise sources in the system. However, the single-ended architecture of the amplifiers employed for the charge processing channels implies a potential problem with noise contributions from power supply sources. Strict system-level constraints leave very little freedom in selecting a power supply structure optimal with respect to: power efficiency, cooling capabilities and power density on modules, but also noise injection to the front-end via the power supply lines. Design of the power supply and distribution system of the Silicon Tracking System in the CBM experiment together with details on the front-end ASICs (STS -XYTER2) and measurement results of power supply and conditioning electronics (selected DC/DC converter and LDO regulators) are presented.

Interface and protocol development for STS read-out ASIC in the CBM experiment at FAIR

This paper presents a proposal of a protocol for communication between the read-out integrated circuit for the STS (Silicon Tracking System) and the Data Processing Board (DPB) at CBM (Compressed Baryonic Matter) experiment at FAIR, GSI (Helmholtzzentrum fuer Schwerionenforschung GmbH) in Germany. The application background, objectives and proposed solution is presented.

A flexible, low-noise charge-sensitive amplifier for particle tracking application

This paper presents characteristics and layout of an integrated charge-sensitive amplifier for the multichannel front-end electronics. The design constraints and requirements are based on the Compressed Baryonic Matter experiment two detector layers: Silicon Tracing System working with silicon strip detectors and the Muon Chamber working with gas detectors. The amplifier is designed for low-power (<;10 mW/channel) and low-noise operation within the operating conditions of two different detectors. The circuit also implements solutions for handling mismatch, detector failure, and corner conditions. The emphasis is also put on the power rail design and analysis of leakage current impact on noise.