Peijun Ding

Oxidation of Ta diffusion barrier layer for Cu metallization in thermal annealing

Abstract This work examines the thermal stability of Ta barrier layer for Cu metallization with the effect of oxygen. The Cu/Ta/SiO 2 /Si films were annealed at temperatures ranging from 400 to 600°C under various vacuum conditions. Transmission electron microscopy has been performed to characterize the microstructure of the films after annealing. The results show that an amorphous interlayer of oxide between Cu and Ta can be formed at 400°C in a vacuum of 10 −2 mbar. X-Ray energy dispersive spectroscopy and electron energy loss spectroscopy confirm that this interlayer is tantalum oxide. This interlayer transformed into a crystalline phase of Ta–Cu oxide at 600°C. In addition, formation of tantalum oxide interlayer is more thermodynamically favorable than that of copper oxide layer at the Cu/Ta interface. Growth of the amorphous interlayer is atmosphere-dependent, as evidenced by the thickness of tantalum oxide being decreased with better vacuum or argon gas. This observation suggests that the oxidation source may arise from the annealing atmosphere rather than from interior SiO 2 . Furthermore, it has been observed that oxygen diffuses along grain boundaries in copper films to cause tantalum oxidation.

Deposition of copper by using self-sputtering

A magnetron sputtering source using sustained self-sputtering has been developed for uniform deposition of copper on large wafers (200 mm in diameter). Usually, Ar gas is used in sputter deposition. In sustained self-sputtering, no Ar gas was used for deposition, the sputtered Cu atoms were ionized in the magnetron plasma, and some Cu ions were accelerated to sputter more Cu atoms out of the target. In this work, the magnetron was optimized to allow sustained self-sputter deposition of Cu on 200 mm wafers with reasonable power (9–12 kW). When sputtering a target of 325 mm in diameter, the minimum power density to sustain plasma without using Ar gas was found to be 10.8 W/cm2. This was much lower than the threshold power density reported in the literature. A chamber employing a large spacing between the target and wafer (16 cm) was used. The resulting deposition rate was about 320 nm/min, when a 12 kW of dc power was applied. The standard deviation in film thickness was less than 2.5% in our limited experi...

The effect of oxygen in the annealing ambient on interfacial reactions of Cu/Ta/Si multilayers

Abstract Interfacial reactions of Cu/Ta/Si multilayers after thermal treatment were investigated using transmission electron microscopy. The Cu and Ta films were deposited onto Si wafer by ionized metal plasma technique. The samples were then annealed at 400, 500, 550 and 600°C in purified Ar atmosphere for 30 min. The effect of oxygen in the atmosphere on the thermal stability is studied. An interlayer of Ta oxide was observed between Cu and Ta after annealing at 400, 500 and 550°C. It is evident that oxygen as residual gas from furnace ambient can diffuse through Cu grain boundaries to form the Ta oxide layer. After annealing at 600°C, Si reacted with Ta to form TaSi 2 at the interface of Ta and Si, in the meantime Cu 3 Si with surrounding SiO 2 formed in the Si substrate. The thermal stability of the Cu/Ta/Si samples was also examined in a two-step annealing treatment of 400°C for 30 min, followed by 600°C for 30 min. Even though interlayers of crystalline Ta–Cu oxide and Ta silicide were formed, Cu silicides were not observed. Formation of TaO x interlayer at the first stage of 400°C annealing may inhibit Cu diffusion into the Si substrate in the second stage of the 600°C annealing process.

Room Temperature Self-Annealing of Electroplated and Sputtered Copper Films

Self-annealing properties of electroplated and sputtered copper films at room temperature were investigated in this study, in particular, the effect of copper film thickness, electrolyte systems used, as well as their level of organic additives for electroplating. Real-time grain growth was observed by transmission electron microscopy. Sheet resistance and X-ray diffraction measurements further confirmed the recrystallization of the electroplated copper film with time. The recrystallization of electroplated films was then compared with that of sputtered copper films.

Advanced Cu barrier/seed development for 65nm technology and beyond

A novel PVD sputtering source has been developed based on a high power-density concept. The new sputtering source dramatically increases the metal ion traction which improves TaN/Ta barrier and Cu seed step coverage and gap fill capability in Cu metallization. Successful ECP gap fill has been achieved on the most aggressive features currently available - 0.08/spl mu/m 6:1 aspect ratio vias - when a 300/spl Aring/ Cu seed layer is deposited with this new source. Electrical test results based on the testing structure of 90nm technology node including parametric and stress migration, are equivalent or better than current processes. The new source will further extend the lifetime of PVD in the IC industry.

IMP Ta/Cu seed layer technology for high-aspect-ratio via fill by electroplating, and its application to multilevel single-damascene copper interconnects

Filling of high aspect ratio vias with electroplated copper requires smooth and continuous seed layer whereas prevention of copper diffusion into the adjacent dielectric requires adequate coverage of the barrier along the via sidewalls. Conventional PVD DC magnetron techniques were found to be inadequate for this application, because of insufficient step coverage especially that of Cu on the sidewalls of the high aspect ratio vias, and its agglomeration into discontinuous islands. Ionized metal plasma (IMP) based PVD technology provided superior step coverage of Ta and Cu because of the directionality of the deposited atoms and utilization of ion bombardment to sputter material from the bottom of the via to the sidewalls, thus yielding continuous and conformal barrier and seed layers. Furthermore, the seed layer morphology especially the roughness of the film on the sidewall was found to be quite sensitive to the deposition temperature. The seed layer thickness and film morphology, as well as other deposition parameters as the ratio of coil RF & target DC plasma powers, Ar sputtering pressure, wafer bias and the Ar sputter etch prior to barrier deposition, were all found to affect the subsequent via filling by electroplating. Optimization of the processes enabled filling of high aspect ratio vias. Manufacturability and the process window for the barrier/seed layer processes was evaluated by extended runs and DOEs. The technology was successfully integrated into a multilevel interconnect scheme utilizing Cu plugs, and Cu damascene lines. The via resistance of the Cu plug using this metallization scheme, was found to be significantly lower than that of W plug currently used for Al interconnects. The cost of ownership (COO) of the IMP Ta/Cu seed layer was determined to be significantly lower compared to the current state-of- the-art IMP Ti/CVD TiN liner for W plug.

Study of metal gate deposition by magnetron sputtering

A systematic study on metal gate deposition by magnetron sputtering is presented. The authors compared the interface trap density (Dit) in metal-oxide-semiconductor capacitors with metal gate deposited by either conventional magnetron sputtering, atomic layer deposition followed by conventional sputter deposition, or a newly developed magnetron sputtering technology. The results indicate that the new sputtering technology can minimize plasma damage to the underlying ultrathin dielectric film and achieve Dit values of less than 1011cm−2eV−1. Experimental data on plasma characterization using ion collectors and Langmuir probe are presented. The effects of metal gate deposition methods, dielectric film thickness, and sputtering parameters such as sputtering power, pressure, and pulsed dc sputtering are discussed. It is found that pulsed dc sputtering generates higher Dit values. In the new sputtering process, the flux and the energy of the ions arriving at the substrate surface are several times lower, and t...

A new PVD sputtering source for metal gate application

A new PVD source for metal gate applications has been systematically characterized. Results from the study indicate that the new source provides very low trap density (<1 times 1011/cm2 eV), excellent film thickness (and sheet resistance) non-uniformity (<1% 1sigma) and a wide range in deposition rates (from 0.4 Aring/s to 6 Aring/s), making it suitable for depositing metal films directly on gate oxides in 45nm and 32nm technology nodes

Nanoscale-level dielectric property image of low-k dielectric materials for copper metallization using energy-filtered TEM

The dielectric properties of low-k material have been characterized using image-spectrum technique via Kramers- Kronig analysis. Quantitative analysis of experimental image-spectrum has been improved using two new quantitative methods. FFT interpolation and maximum entropy deconvolution were successfully used to solve the two problems: under- sampling and loss of energy resolution in image-spectrum technique, respectively. In this study, carbonated SiO2 based low-k dielectric layer designed for copper metallization was used as a demo example. We show that the reconstructed image-spectrum obtained from ESI series images can be quantified with the same accuracy as conventional EELS spectrum. We also developed a new method to quantitatively determine dielectric constant for low-k materials. We have determined the thickness of the carbonated SiO2 based low-k material using extrapolated thickness method from the materials of known dielectric constants. The dielectric function map can be deduced from 2-dimensional reconstructed single scattering spectra with providing the information of thickness via Kramers-Kronig analysis. We proposed a four-dimensional data presentation for revealing the uniformity of the energy dependent property. The accuracy of our methods depends on the thickness determination and on the quality of the reconstructed spectra from the image series. Finally, the dielectric property of carbonated SiO2 based low-k material after annealed process was investigated using Kramers-Kronig analysis to found the relationship of dielectric constant and material density.

Cu barrier/seed technology development for sub-0.10 micron copper chips

Advanced PVD technologies have been reviewed for copper barrier-seed applications for different device nodes. Each new device generation requires improved step coverage and reduced overhang. With each shift in deposition technology, there have been process and hardware advancements to meet decreasing feature sizes and increasing aspect ratios. The extension of PVD to 0.1 /spl mu/m has delayed the need for a CVD barrier and seed solution. However, PVDs limitations in step coverage, and the introduction of porous low-k dielectrics may necessitate a transition to CVD barriers below 0.10 /spl mu/m. The process integration of SIP-Cu and a proven barrier solution TDMAT (tetrakis dimethyl amino titanium)-based CVD TiSiN is also discussed in this paper.