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Dive into the research topics where Suraj Rengarajan is active.

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Featured researches published by Suraj Rengarajan.


MRS Proceedings | 1999

Room Temperature Self-Annealing of Electroplated and Sputtered Copper Films

Michelle Chen; Suraj Rengarajan; Peter Hey; Yezdi Dordi; Hong Zhang; Imran Hashim; Peijun Ding; Barry Chin

Self-annealing properties of electroplated and sputtered copper films at room temperature were investigated in this study, in particular, the effect of copper film thickness, electrolyte systems used, as well as their level of organic additives for electroplating. Real-time grain growth was observed by transmission electron microscopy. Sheet resistance and X-ray diffraction measurements further confirmed the recrystallization of the electroplated copper film with time. The recrystallization of electroplated films was then compared with that of sputtered copper films.


international interconnect technology conference | 2002

Barrier crystallographic texture control and its impact on copper interconnect reliability

Jay Chen; S. Parikh; T. Vo; Suraj Rengarajan; T. Mandrekar; Peijun Ding; Ling Chen; Roderick Craig Mosely

The impacts of barrier micro-structure on Cu seed and electro copper plating (ECP) film have been investigated in terms of seed sheet resistance (R/sub s/) stability, crystal orientation, and wetting properties; ECP film surface morphology and CMP defects. We have studied the effect of these parameters using 4-point probe, X-ray diffraction (XRD), scanning electron microscopy (SEM), and SEM vision. We also studied barrier impact on via resistance and interconnect reliability using E-test measurement and stress migration test. It was found that barrier layer micro-structure can manipulate seed layer and ECP film properties, which affect E-test performance. The seed layer deposited on highly <110>-oriented /spl alpha/-Ta underlayer shows better Cu <111> orientation, resulting in a seed with stable R/sub s/, better wetting properties, smoother ECP film, and lower defects. In addition, it shows lower via resistance and better interconnection reliability.


international conference on solid state and integrated circuits technology | 2006

A new PVD sputtering source for metal gate application

Peijun Ding; Dave Liu; Mengqi Ye; Suraj Rengarajan; Jianming Fu; Zheng Xu

A new PVD source for metal gate applications has been systematically characterized. Results from the study indicate that the new source provides very low trap density (<1 times 1011/cm2 eV), excellent film thickness (and sheet resistance) non-uniformity (<1% 1sigma) and a wide range in deposition rates (from 0.4 Aring/s to 6 Aring/s), making it suitable for depositing metal films directly on gate oxides in 45nm and 32nm technology nodes


Archive | 2002

Precleaning process for metal plug that minimizes damage to low-κ dielectric

Barney M. Cohen; Suraj Rengarajan; Kenny King-Tai Ngan


Archive | 2001

Barrier applications for aluminum planarization

Shri Singhvi; Suraj Rengarajan; Peijun Ding; Gongda Yao


Archive | 2002

Method of depositing a TaN seed layer

Xianmin Tang; Praburam Gopalraja; Suraj Rengarajan; John C. Forster; Jianming Fu; Peijun Ding


Archive | 2004

Compensation of spacing between magnetron and sputter target

Peijun Ding; Daniel C. Lubben; Ilyoung Richard Hong; Michael Miller; Hsien-Lung Yang; Suraj Rengarajan; Arvind Sundarrajan; Goichi Yoshidome


Archive | 2001

Monitoring process for oxide removal

Haojiang Li; Peijun Ding; Suraj Rengarajan


Archive | 2005

Method of depositing a tantalum nitride/tantalum diffusion barrier layer system

Peijun Ding; Zheng Xu; Hong Zhang; Xianmin Tang; Praburam Gopalraja; Suraj Rengarajan; John C. Forster; Jianming Fu; Tony Chiang; Gongda Yao; Fusen E. Chen; Barry L. Chin; Gene Y. Kohara


Archive | 2005

Method of depositing low resistivity barrier layers for copper interconnects

Peijun Ding; Zheng Xu; Hong Zhang; Xianmin Tang; Praburam Gopalraja; Suraj Rengarajan; John C. Forster; Jianming Fu; Tony Chiang; Gongda Yao; Fusen E. Chen; Barry L. Chin; Gene Y. Kohara

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