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Dive into the research topics where Peizhen Yang is active.

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Featured researches published by Peizhen Yang.


Microelectronics Reliability | 2010

Observation of halo implant from the drain side reaching the source side and vice versa in extremely short p-channel transistors

W.S. Lau; Peizhen Yang; Eng Hua Lim; Yee Ling Tang; Seow Wei Lai; V.L. Lo; Soh Yun Siah; Lap Chan

Abstract The merging of halo implants from the drain side and the source side creates a maximum in the magnitude of the threshold voltage and thus a minimum in the off-current in the metal-oxide-semiconductor transistors. This paper demonstrates that the halo implant from the drain side can cross-over to the source side and vice versa for the look-ahead transistor test structures (transistor test structures with gate length smaller than that of the target transistor). The phenomenon of the cross-over of halo implant is more readily observed in PMOS transistors compared to NMOS transistors because for the same mask gate length, the effective channel length of PMOS transistor tends to be smaller than that of NMOS transistor. The advantage of the cross-over of halo implants can be understood as follows. Since the hole mobility is smaller than the electron mobility in silicon, PMOS transistor tends to have smaller on-current ( I on ) than NMOS transistor. The on-current can be increased by using PMOS transistor with smaller mask gate length compared to the NMOS transistor. However, this approach will make the PMOS transistor very sensitive to the statistical variation in the gate electrode length during manufacturing. By making use of the above reported phenomenon, PMOS transistor can be made shorter without running into manufacturing control problem, resulting in bigger I on but the penalty is that the I off will become significantly higher.


Applied Physics Letters | 2008

Switching from ⟨110⟩ to ⟨100⟩ orientation increases both the on current and off current of p-channel metal-oxide semiconductor transistors

Peizhen Yang; W. S. Lau; V. Ho; B. K. Lim; S. Y. Siah; L. Chan

If the on current of p-channel metal-oxide semiconductor (PMOS) transistors fabricated on (100) silicon substrate can be easily increased by switching from ⟨110⟩ to ⟨100⟩ orientation because of faster hole transport in the “on state,” it is natural to expect that this switching can also increase the off current because of faster hole transport in the “off state.” Indeed we managed to observe this experimentally for relatively long PMOS transistors. In this letter, we will also show that there is an overall performance improvement in PMOS transistors despite the increase in both on current and off current.


Applied Physics Letters | 2008

Reduced boron lateral ion channeling in very short p-channel transistors by switching from ⟨110⟩ to ⟨100⟩ channel orientation

W. S. Lau; Peizhen Yang; V. Ho; B. K. Lim; S. Y. Siah; L. Chan

The on-current of p-channel transistors fabricated on (100) Si substrate can be easily increased by switching from ⟨110⟩ to ⟨100⟩ channel orientation because of faster hole transport. In this paper, we pointed out that there is also a reduction in the gate-to-source/drain overlap, resulting in an increase in the effective channel length for p-channel transistors. Our experimental observation can be explained by a reduction in boron lateral ion channeling due to this switch.


Applied Physics Letters | 2007

Effect of tensile stress on the various components of the off current of n-channel metal-oxide-semiconductor transistors

Peizhen Yang; W. S. Lau; V. Ho; C. H. Loh; S. Y. Siah; L. Chan

The authors found that tensile stress actually slightly increases the on current and the subthreshold off current but it slightly decreases the gate leakage current and the drain junction leakage current for n-channel metal-oxide-semiconductor transistors. For short transistors, the subthreshold off current dominates over the other two components of the off current such that tensile stress slightly increases both the on current and the off current. However, in the on current versus the logarithm of off current plot, tensile stress increases the on current for a constant off current such that the overall effect of tensile stress is an improvement.


Applied Physics Letters | 2009

Improvement of subthreshold swing of n-channel transistor by uniaxial tensile stress due to a quantum mechanical mechanism instead of physical thinning

W. S. Lau; Peizhen Yang; Seow Wei Lai; V.L. Lo; Soh Yun Siah; L. Chan

Physical thinning of the gate dielectric due to uniaxial tensile stress is expected to improve the subthreshold swing (Sts) of both n-channel and p-channel metal-oxide-semiconductor (MOS) transistors. However, experimentally, we observed a small improvement in Sts of n-channel MOS transistors but a small degradation in Sts of p-channel MOS transistors due to the application of uniaxial tensile stress. Uniaxial tensile stress modifies the out-of-plane effective mass of electrons or holes, resulting in a change in Sts, which can be predicted by quantum mechanics.


international conference on electron devices and solid-state circuits | 2008

Effective channel length increased due to switching from ≪110≫ to ≪100≫ orientation for PMOS transistors fabricated by 65 nm CMOS technology

W.S. Lau; Peizhen Yang; V. Ho; B.K. Lim; S.Y. Siah; L. Chan

The on-state current of PMOS transistors fabricated on (100) Si substrate can be easily increased by switching from <110> to <100> orientation because of faster hole transport. In addition, PMOS transistors also become slightly ldquolongerrdquo. An experimental estimation of the increase of the effective channel length of the order of nm was made in PMOS transistors fabricated by 65 nm low-power CMOS technology. This can cause a noticeable drop in off current for short PMOS transistors.


international conference on electron devices and solid-state circuits | 2008

Region of nearly constant off current versus gate length characteristics for sub-0.1 μm low power CMOS technology

W.S. Lau; Peizhen Yang; Edwin T.L. Ng; Z.W. Chian; V. Ho; S.Y. Siah; L. Chan

A minimum in the off current versus gate length characteristics can occur at a threshold voltage maximum for MOS transistors. Sometimes, instead of a minimum, an inflection point can occur at a threshold voltage maximum. We observed that more than one minimum can be experimentally seen. These multiple off current minima can interact with each other and inflection points to create a large range of gate lengths with around the same off current.


Applied Physics Letters | 2010

Physics of electron mobility independent of channel orientation in n-channel transistors based on (100) silicon wafers and its experimental verification

W. S. Lau; Peizhen Yang; T. P. Chen; S. Y. Siah; L. Chan

The six degenerate ellipsoid model can be used to study the effects of channel orientation on electron mobility. However, this approach has two assumptions: (i) the conduction band minimum near the interface between gate dielectric and silicon channel is the same as that of bulk silicon, (ii) the momentum relaxation time is independent of the channel orientation. This letter shows that the effective conductivity electron mass of (100) surface-oriented silicon is independent of channel orientation even though the actual conduction band minimum may be slightly different from the six degenerate ellipsoid model. Experimental data are provided to support our theory.


Microelectronics Reliability | 2008

A study of the linearity between Ion and log Ioff of modern MOS transistors and its application to stress engineering.

W. S. Lau; Peizhen Yang; C.W. Eng; V. Ho; C.H. Loh; Soh Yun Siah; D. Vigar; Lap Chan


Microelectronics Reliability | 2008

An explanation of the dependence of the effective saturation velocity on gate voltage in sub-0.1 μm metal–oxide–semiconductor transistors by quasi-ballistic transport theory

W. S. Lau; Peizhen Yang; V. Ho; L.F. Toh; Y. Liu; Soh Yun Siah; Lap Chan

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V. Ho

Chartered Semiconductor Manufacturing

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W. S. Lau

Nanyang Technological University

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Soh Yun Siah

Chartered Semiconductor Manufacturing

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Lap Chan

Chartered Semiconductor Manufacturing

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W.S. Lau

Nanyang Technological University

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B. K. Lim

Chartered Semiconductor Manufacturing

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C.H. Loh

Chartered Semiconductor Manufacturing

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S.Y. Siah

Chartered Semiconductor Manufacturing

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