Pengfei Liao

Digital Assistant Power Integrated Technologies for PMU in Scaling CMOS Process

Several novel digital assistant power integrated technologies (DAPITs) for power management unit (PMU) to reduce the designing complexity, as well as to keep good performance in scaling CMOS process, are proposed in this paper. The DAPITs include segment power driving with pulse skip modulation/pulse width modulation and loop regulating with digital regulation circuit for dc-dcs in PMU, calibrating digital-to-analog converter (DAC) with resistance compensation network for dynamic voltage scaling (DVS), and separating phase clock for multi-dc-dcs in PMU. With these DAPITs, the efficiencies and output accuracies of dc-dcs are increased, the DVS signal sent by DAC is linear, and current ripples in PMU are reduced. In this paper, a PMU embedded into system-on-a-chip (SoC) is designed based on a 0.13-μm CMOS process. The designed PMU includes four dc-dc buck converters and two LDOs. This paper introduces the top structure of the PMU and the main proposed DAPITs. Simulation and test results show that the output voltages of the dc-dc converters in the PMU can be changed by external resistors and regulated from 0.7 to 1.8 V stepped with 25 mV by SoC load through interface. And the maximum efficiency of the dc-dcs with DVS in the PMU is more than 90%, while, with an external resistor, it can reach to 95%.

A miniature high-efficiency fully digital adaptive voltage scaling buck converter

A miniature high-efficiency fully digital adaptive voltage scaling (AVS) buck converter is proposed in this paper. The pulse skip modulation with flexible duty cycle (FD-PSM) is used in the AVS controller, which simplifies the circuit architecture (<170 gates) and greatly saves the die area and the power consumption. The converter is implemented in a 0.13-μm one-poly-eight-metal (1P8 M) complementary metal oxide semiconductor process and the active on-chip area of the controller is only 0.003 mm2, which is much smaller. The measurement results show that when the operating frequency of the digital load scales dynamically from 25.6 MHz to 112.6 MHz, the supply voltage of which can be scaled adaptively from 0.84 V to 1.95 V. The controller dissipates only 17.2 μW, while the supply voltage of the load is 1 V and the operating frequency is 40 MHz.

A compact ADPLL based on symmetrical binary frequency searching with the same circuit

A compact all-digital phase-locked loop (C-ADPLL) based on symmetrical binary frequency searching (BFS) with the same circuit is presented in this paper. The minimising relative frequency variation error Δη (MFE) rule is derived as guidance of design and is used to weigh the accuracy of the digitally controlled oscillator (DCO) clock frequency. The symmetrical BFS is used in the coarse-tuning process and the fine-tuning process of DCO clock frequency to achieve the minimum Δη of the locked DCO clock, which simplifies the circuit architecture and saves the die area. The C-ADPLL is implemented in a 0.13 μm one-poly-eight-metal (1P8M) CMOS process and the on-chip area is only 0.043 mm2, which is much smaller. The measurement results show that the peak-to-peak (Pk-Pk) jitter and the root-mean-square jitter of the DCO clock frequency are 270 ps at 72.3 MHz and 42 ps at 79.4 MHz, respectively, while the power consumption of the proposed ADPLL is only 2.7 mW (at 115.8 MHz) with a 1.2 V power supply. The measured Δη is not more than 1.14%. Compared with other ADPLLs, the proposed C-ADPLL has simpler architecture, smaller size and lower Pk-Pk jitter.

Embedded current amplifier compensation for large-capacitive-load low-power two-stage amplifier

An embedded current amplifier compensation (ECAC) for large-capacitive-load low-power two-stage amplifier is presented in this paper with detailed theoretical analysis. With the embedded current amplifier in the first stage, the non-dominant pole determined by the load capacitor is pushed to higher frequencies while the GBW reduction is avoided, hence the capacity of driving capacitive load is improved. The size of compensation capacitor is also reduced significantly to save the overall chip area. Furthermore, the system offset is minimized due to the good symmetry of the first stage. The proposed circuit is designed and simulated in 0.13μm standard CMOS process. Simulation results show that the ECAC amplifier, driving an 800pF capacitive load, achieves a GBW of 4.2MHz while dissipating 200μW power with a compensation capacitor of only 1.5pF.

Embedded advanced capacitor multiplier compensation for two-stage amplifier with large capacitive loads

An embedded capacitor multiplier compensation (EACMC) for two-stage amplifier with large capacitive loads is presented in this paper with detailed theoretical analysis. Two voltage-controlled current sources are inserted in the proposed capacitor multiplier which is embedded in the first stage. With the advanced capacitor multiplier, the gain factor of the multiplier is enhanced and the compensation capacitor is reduced significantly. Furthermore, the GBW achieved is extended as a result. The proposed circuit is designed and simulated in 0.13μm standard CMOS process. Simulation results show that the EACMC amplifier, driving a 1200 pF capacitive load, achieves a GBW of 1.51 MHz while dissipating 154 μW power with a compensation capacitor of only 0.85 pF.

Embedded current amplifier compensation for three-stage amplifiers with large capacitive loads

An embedded current amplifier compensation (ECAC) for threestage amplifiers with large capacitive loads is presented in this paper. Two current amplifiers are embedded into the first stage. The compensation capacitor is connected to the input of the current amplifier rather than the output of the first stage, which enables the non-dominant complex poles of the ECAC amplifier to be located at high frequencies for bandwidth extension; in addition, the compensation capacitor required is greatly reduced. The amplifier has been fabricated in a 0.13μm CMOS process. When driving a 2000 pF capacitive load, the ECAC amplifier achieves 1.85MHz gain-bandwidth product by dissipating 33.6 μW power at 1.2V supply and using total compensation capacitance of only 0.8 pF.

An Adaptive Voltage Scaling DC-DC Converter with Embedded Minimum Energy Point Tracking

An Adaptive Voltage Scaling DC-DC Converter with Embedded Minimum Energy Point Tracking technique is presented in this paper. Three techniques, named Minimum Energy Point (MEP) Tracking (MEPT), Adaptive Voltage Scaling (AVS) and Pulse Skip Modulation (PSM), are combined in the proposed converter. The circuit is simulated in a 0.13μm standard CMOS technology, the simulation result shows that, the output voltage of the converter varies from 0.2V~1.5V. When the frequency ranges from 25kHz to 125MHz, furthermore, the circuit can successfully tracks the MEP at 575mV@20MHz and the MEP at 0.5V@10MHz.

A Phase Lead Compensation block for DC-DC converters in PMU

A novel Phase Lead Compensation (PLC) for DC-DC converters in Power Management Unit (PMU) is presented in this paper. Capacitor multiplier technique and the input differential pair are implemented. With this PLC, a compact-size buck converter with a high negative Power Supply Ratio Rejection (PSRR-) is achieved. The converter is simulated in a 0.13μm CMOS process. Simulation results show the PSRR- has increased by 75db compared to conventional PLC converter, and the phase margin can reach 60° with smaller passive components (C=3.7pf, R=600k).