Shaowei Zhen

A high efficiency synchronous buck converter with adaptive dead time control for dynamic voltage scaling applications

An integrated synchronous buck converter with adaptive dead time controlled driver is presented in this paper. The integrated synchronous buck converter works in 2MHz PWM mode and the output voltage can be programmed by digital interface, which is suitable for powering the processor core and internal memory with dynamic voltage scaling (DVS) capability. The controller provides 0 and 100% duty cycles during DVS, maximizing tracking speed while saving power. The driver circuit detects body diode conduction by a proper biased N-type transistor. The synchronous N-type power MOS is turned on at the falling edge of body diode conduction detection in both DCM and CCM. The P-type power MOS is turned on at the falling edge of dead time detection in CCM. As a result, the dead time varies according to the load current, while the conduction time of the body diode in the synchronous power MOS is approaching to the delay of logic circuit and gate driver. The dead time control logic and gate driver are designed with low time lag to minimize body diode conduction time. Experimental results show that the converter can achieve fast reference tracking and the conversion efficiency is up to 90%.

A high energy efficiency PSM/PWM dual-mode for DC-DC converter in portable applications

Based on the Energy Conservation Rule, an Unideal Energy Balance (UEB) model of a DC-DC converter in Discontinuous Conduction Mode (DCM) is built and the energy efficiency of the power converter is studied. A high energy efficiency PSM/PWM dual-mode for DC-DC converter is proposed in this paper after compared the energy efficiencies of the converter in Pulse Skip Modulation (PSM) mode and Pulse Width Modulation (PWM) mode separately. According to the real time value of energy efficiency, PSM mode is adopted for light loads, while, PWM mode is used for moderate or heavy loads in the proposed PSM/PWM dual-mode, that make the converter keep high energy efficiency in the whole variable loads range. The real time value of energy efficiency is easy to be calculated by the DSP/CPU in the System on Chip (SoC) of a portable appliance and transferred through the data interface I2C.

On-chip compensated error amplifier for voltage-mode buck converters

An on-chip compensated error amplifier in a voltage-mode buck converter is proposed in the paper. The compensated error amplifier is composed of two blocks, unit gain zero generation block and gain block, realizing phase shift and gain of the feedback loop, respectively. Compared to conventional type III compensated error amplifier in voltage-mode buck converter, the proposed circuit has much smaller passive component values, enabling full integration of the voltage mode buck converter in SoC. The converter is designed in 0.13µm CMOS process, operating typically at 1.5 MHz pulse width modulation (PWM). The simulation results show the converter with on-chip compensated error amplifier achieves both 0.3% load regulation and 10µs load step response time for load step between 200mA and 700mA.

Digital Assistant Power Integrated Technologies for PMU in Scaling CMOS Process

Several novel digital assistant power integrated technologies (DAPITs) for power management unit (PMU) to reduce the designing complexity, as well as to keep good performance in scaling CMOS process, are proposed in this paper. The DAPITs include segment power driving with pulse skip modulation/pulse width modulation and loop regulating with digital regulation circuit for dc-dcs in PMU, calibrating digital-to-analog converter (DAC) with resistance compensation network for dynamic voltage scaling (DVS), and separating phase clock for multi-dc-dcs in PMU. With these DAPITs, the efficiencies and output accuracies of dc-dcs are increased, the DVS signal sent by DAC is linear, and current ripples in PMU are reduced. In this paper, a PMU embedded into system-on-a-chip (SoC) is designed based on a 0.13-μm CMOS process. The designed PMU includes four dc-dc buck converters and two LDOs. This paper introduces the top structure of the PMU and the main proposed DAPITs. Simulation and test results show that the output voltages of the dc-dc converters in the PMU can be changed by external resistors and regulated from 0.7 to 1.8 V stepped with 25 mV by SoC load through interface. And the maximum efficiency of the dc-dcs with DVS in the PMU is more than 90%, while, with an external resistor, it can reach to 95%.

Digital Error Corrector for Phase Lead-Compensated Buck Converter in DVS Applications

Modern low-power system on a chip needs direct current converter with dynamic voltage scaling (DVS) ability for core power supply. The converter output should be accurate voltage across the full load current and voltage scaling range. An integrated buck converter for DVS application is proposed in this brief. Voltage mode phase lead compensation is implemented in the converter, with much smaller passive components than conventional type-III compensation. To improve accuracy, the output voltage error accompanied with load current and reference voltage caused by finite loop gain in analog control loop is corrected by the digital error corrector. The output voltage is compared by two comparators whose threshold voltage is about 10 mV above and below the reference voltage, respectively. The duty cycle is slightly adjusted by finite state machine according to outputs of the two comparators. Experimental results show that the converter is well regulated over an output range of 0.7-1.8 V, with step voltage of 25 mV. When load current suddenly changes between 170 and 500 mA, the overshoot and undershoot voltage are 32 and 50 mV, respectively. Load regulation is maintained about 1% throughout the full load range. The voltage error is within ±10 mV in the voltage scaling range.

A voltage mode power converter with the function of digitally duty cycle tuning

A voltage mode power converter with the function of digitally duty cycle tuning is presented. Enough loop gain is required to guarantee a good load regulation. In the proposed design, the load regulation can be improved through digitally duty cycle tuning, based on phase lead compensated voltage mode power converters. The whole circuit is implemented in a 0.13µm 1P8M CMOS process. The simulation results show that the output voltages deviation can be controlled within ±10mV when the load current steps from 200mA to 1.65A, and a 14µV/mA load regulation can be obtained.

An adaptive voltage scaling buck converter based on improved pulse skip modulation

A novel adaptive voltage scaling (AVS) buck converter based on improved pulse skip modulation (IPSM) is proposed in this paper. Pulse skip modulation is used for AVS converter for the first time. The controller of the buck converter includes a delayline, a slacktime detector, a finite-state machine (FSM) and a hybrid digital pulse width modulator (DPWM) which is used to produce a sequence of pulses whose duty cycle is alterable and frequency is fixed according to the input. Compared to AVS buck converter based on pulse width modulation (PWM), AVS buck converter based on IPSM is more efficient under light loads. Meanwhile, the structure of the controller of the proposed AVS buck converter is simple and can be realized by digital design methodology and process, which make the controller easy to be integrated into SoC. The converter is designed in 0.13 µM CMOS process, operating typically at 1.5 MHz. The simulation results show that the output voltage of the converter is adjusted ranged from 0.7 V to 1.5 V to the varied frequency ranged from 25 MHz to 100 MHz of the digital load circuit, which can save the power consumption effectively. The ripple of the output voltage of the buck converter is only 7–24 mV. The layout size of the controller is only 69 µm × 165 µm which is very small.

A miniature high-efficiency fully digital adaptive voltage scaling buck converter

A miniature high-efficiency fully digital adaptive voltage scaling (AVS) buck converter is proposed in this paper. The pulse skip modulation with flexible duty cycle (FD-PSM) is used in the AVS controller, which simplifies the circuit architecture (<170 gates) and greatly saves the die area and the power consumption. The converter is implemented in a 0.13-μm one-poly-eight-metal (1P8 M) complementary metal oxide semiconductor process and the active on-chip area of the controller is only 0.003 mm2, which is much smaller. The measurement results show that when the operating frequency of the digital load scales dynamically from 25.6 MHz to 112.6 MHz, the supply voltage of which can be scaled adaptively from 0.84 V to 1.95 V. The controller dissipates only 17.2 μW, while the supply voltage of the load is 1 V and the operating frequency is 40 MHz.

A dual-mode digitally controlled converter for synchronous buck converters operating over wide ranges of load currents

A monolithic digitally controlled Pulse Width Modulation/Pulse Skip Modulation (PWM/PSM) dual-mode converter for synchronous buck DC/DC converters is proposed in this paper. The controller operates in PWM during Continuous Conduction Mode(CCM) at 2MHz switching frequency while PSM is adopted to reduce switching loss at Discontinuous Conduction Mode(DCM). Several blocks, including a low power Analog-Digital Converter (ADC), a high resolution and linearity Digital Pulse Width Modulator (DPWM) with a digital DLL and a PSM controller, are described in detail. The converter is simulated in a standard 0.13μm CMOS process, and the simulation results show the high efficiency over a wide of load and fast transient response of digital converter.

A fast and energy efficient binary-to-pseudo CSD converter

The canonical signed digit (CSD) coding is widely used in digital arithmetic operations due to its property that there is no adjacent nonzero digits in the encoded numbers. However, the benefits of the CSD coding may be faded because of the recursive conversion process from the binary representations. This paper presents a novel pseudo CSD coding method, which takes the merits of CSD, while simplifies the conventional conversion process. The simulation results indicate that the proposed converter can achieve at least 31.8% speed improvement and 42.9% energy reduction for a 16-bit binary operand at 1.2V in a 0.13-μm CMOS technology. It could run even faster than the competitors when the operand length increases.