Peter D. Hoh

Unpinned gallium oxide/GaAs interface by hydrogen and nitrogen surface plasma treatment

The Fermi level at the Ga oxide/GaAs interface has been unpinned by rf plasma cleaning the GaAs surface in H2 and N2. Following plasma cleaning, a Ga oxide film is reactively electron beam deposited onto the substrate. Metal‐oxide‐semiconductor (MOS) capacitors fabricated on these structures show good high‐frequency capacitance‐voltage characteristics. This indicates that the density of interface states has been reduced to ∼1011 eV−1 cm−2. The MOS capacitors are found to be stable in air after several months.

Characterization of GaAs self‐aligned refractory‐gate metal‐semiconductor field‐effect transistor (MESFET) integrated circuits

GaAs metal‐semiconductor field‐effect transistors (MESFETs) and other integrated‐circuit elements were characterized by including extensive process test sites on wafers with digital logic and memory circuits. A self‐aligned, refractory‐gate enhancement/depletion (E/D) process was employed which included 47SiF+ channel and source/drain implants, capless arsenic overpressure furnace annealing, WSi0.11 gate metal with in situ sputter cleaning, Ni‐Au‐Ge ohmic contacts, Si3N4 or SiO2 insulation, and Ni‐Au wiring. On‐water threshold voltage standard deviations as low as 31 mV for 1‐μm E‐FETs and 49 mV for 1‐μm D‐FETs were measured using 51‐mm standard semi‐insulating liquid‐encapsulated Czochralski GaAs substrates. Threshold voltage control from wafer to wafer was of order 100 mV. Schottky diode barrier height was about 0.73 eV with an ideality of 1.2, although small self‐aligned Schottky gates often showed excess conduction believed to occur at the gate edges. FET square‐law coefficient, subthreshold leakage, ...

Challenge of 1-Gb DRAM development when using optical lithography

The traditional lithographic approach employed by the semiconductor industry has been to pursue use of advanced prototype optical exposure tools and resists. The benefits of doing so have been: (1) The lithographic process that is used in development more closely resembles the process that will in fact be used to manufacture the chip. (2) The cost of low K1 imaging (phase-masks, off-axis illumination, and surface imaging resist) can be avoided. However with the introduction of 1Gb-dynamic random access memory (DRAM) development, a paradigm shift is being experienced within the optical lithographic community. With 1Gb-DRAMs, the minimum feature size falls irreversibly below the optical wavelength used to image the feature. Such a situation will make low K1 factor imaging unavoidable. With 175 nm groundrules typical for first generation 1G-DRAMs, K1 factors near 0.4 will be common with 0.5 as an upper limit on advanced systems currently in development irrespective of optical wavelength. This paper will cover the selection process, experimental data, and problems encountered in defining and integrating the lithographic process used to support the critical mask levels on 1Gb-DRAM development. Factors considered include: resist, masks, and illuminations via both simulation and experiment. The simulations were conducted with both internal and externally developed software. The experimental data to be reviewed was generated using an experimental 0.6 NA KrF step and scan system provided by Nikon. The resist used is commercially available from the Shipley corporation.

Viability of conventional high-NA KrF imaging for sub-0.25-um lithography

As the competitive pressures of the semiconductor industry drive to feature sizes below 250 nanometer, unconventional imaging approaches are being considered in order to preserve the cost effectiveness of optical lithography. To achieve minimum feature size with a usable process window, phase shift masks, off-axis illumination, and ArF lithography have been investigated with varying degrees of success. Unfortuanely, the maturity and flexibility of such techniques are questionable at this time. This paper investigates the extendibilty of traditional imaging approaches for use in the sub 250 nanometer regime. Aerial image simulations were used to set expectation levels by increasing lens numerical aperture versus prior state of the art exposure systems. Experimental data was then generated with an advanced 0.6 NA excimer laser based step and scan exposure system. Single point per field comparisons are made between simulations and experimental data covering linearity, depth of focus, and exposure dose window for feature sizes between 250 nanometers and 200 nanometers. In addition, data reviewing the ability to extend such performance across a 25 mm by 33 mm field size is reviewed.