Dianne L. Lacey

Unpinned gallium oxide/GaAs interface by hydrogen and nitrogen surface plasma treatment

The Fermi level at the Ga oxide/GaAs interface has been unpinned by rf plasma cleaning the GaAs surface in H2 and N2. Following plasma cleaning, a Ga oxide film is reactively electron beam deposited onto the substrate. Metal‐oxide‐semiconductor (MOS) capacitors fabricated on these structures show good high‐frequency capacitance‐voltage characteristics. This indicates that the density of interface states has been reduced to ∼1011 eV−1 cm−2. The MOS capacitors are found to be stable in air after several months.

Thermal stability of polycrystalline silicon/metal oxide interfaces

The thermal stability of polycrystalline silicon (poly-Si)/ZrO2 interface was significantly enhanced when the poly-Si was plasma deposited using silane heavily diluted in He. With regard to this process, transmission electron microscopy shows a sharp poly-Si/ZrO2 interface that is stable at 1000 °C. When the poly-Si was deposited by chemical vapor deposition using undiluted silane gas, transmission electron microscopy shows strong reactions at the poly-Si/ZrO2 interface when annealed at 1000 °C. The increased stability can be attributed to He dilution, which may prevent hydrogen from reducing the metal oxide. Another explanation may be directly related to He-excited plasma, which is known to produce denser and more stable films.

Properties and thermal stability of the SiO2/GaAs interface with different surface treatments

High quality SiO2 films were deposited by plasma‐enhanced chemical vapor deposition on GaAs wafers which received different surface treatments. It was found that metal‐oxide‐semiconductor (MOS) capacitors which received surface nitridation were unstable under high‐temperature anneal (600 °C). These instabilities are interpreted in terms of free As precipitates at the interface. When, instead, a thin Si layer was deposited on the GaAs surface, stable interfaces were obtained at 600 °C. These MOS capacitors appear to show both deep depletion and inversion.

Lithographically fabricated fiber guides for optical subassemblies

A new optoelectronic packaging technology is presented which permits highly accurate fiber-to-chip alignment at low cost. Instead of the more common methods employed in fabricating optical subassemblies, which use leadframe, precision plastic-molding, or silicon-optical-bench technology, here fiber guides are fabricated in a photoresist by use of standard photolithographic procedures. By this means the fiber guides are directly created on an entire wafer of either VCSELs or receivers, resulting in structures with very tight dimensional tolerances fabricated at very low cost. After dicing, a fiber is interfaced with a chip under computer control using a very simple semiautomatic tool to insert the fiber into the fiber guide. This new technology may be used in the fabrication of a wide variety of single or multi-channel optoelectronic transceivers.