A. Callegari

Physical and electrical characterization of Hafnium oxide and Hafnium silicate sputtered films

Hafnium oxides and hafnium silicate films were investigated as a possible replacement for the SiO2 gate dielectric. Hafnium oxide films were formed by reactive sputtering from a single Hf oxide target in a predominantly Ar atmosphere containing small additions of oxygen. Hafnium silicates were made by adding a He-diluted silane gas for Si incorporation. By changing the silane gas flow, different Si atomic concentrations were incorporated into the Hf oxide films. Depositions were performed with the substrate held at temperatures of 22 °C and 500 °C. The chemical composition of the films was determined with nuclear techniques. Optical reflectivity was used to measure the optical band gap. The film morphology was investigated by transmission electron microscopy (TEM) and the electrical properties were measured with capacitance–voltage and current–voltage measurements using aluminum gate capacitors. TEM and electrical measurement showed that a SiO2 interfacial layer of about 3 nm formed at the Si interface du...

Ultrathin high-K gate stacks for advanced CMOS devices

Reviews recent progress in and outlines the issues for high-K high-temperature (/spl sim/1000/spl deg/C) poly-Si CMOS processes and devices and also demonstrate possible solutions. Specifically, we discuss device characteristics such as gate leakage currents, flatband voltage shifts, charge trapping, channel mobility, as well as integration and processing aspects. Results on a variety of high-K candidates including HfO/sub 2/, Al/sub 2/O/sub 3/, HfO/sub 2//Al/sub 2/O/sub 3/, ZrO/sub 2/, silicates, and AlN/sub y/(O/sub x/) deposited on silicon by different deposition techniques are shown to illustrate the complex issues for high-K dielectric integration into current Si technology.

Effects of interfacial microstructure on uniformity and thermal stability of AuNiGe ohmic contact to n‐type GaAs

As part of the investigation of the use of AuNiGe as the ohmic contact to n‐type GaAs at a high integration level, cross‐sectional transmission electron microscopy was used to explore the uniformity at the metal/GaAs interface and the thermal stability of the AuNiGe contact after the ohmic contact formation. A close relation between spread of the contact resistance and nonuniformity of the interfacial microstructure of the contact was found. Deposition of 5‐nm‐thick Ni as the first layer of the AuNiGe ohmic contact significantly reduced the spread of the contact resistance and led to the formation of a uniform interface without large protrusions. The improvement in uniformity of compound distribution and the reduction of interface roughness are believed to be due to a change in the sequence of alloying reactions, compared to those in the contact without a Ni first layer. This suggests an ideal interface structure for a low resistance AuNiGe ohmic contact after alloying to be a uniform two layer structure: a high density of the NiAs(Ge) grains contacting the GaAs substrate, and a homogeneous β‐AuGa phase close to the top surface. However, due to the existence of β‐AuGa phases with a low melting point of around 375 °C, the thermal stability of the contact at 400 °C is of serious concern. Segregation of the NiAs(Ge) grains was observed after annealing at 400 °C for 10 h, which reduced the contact areas between the NiAs(Ge) grains and GaAs. During subsequent annealing at this temperature for up to 90 h, liquidlike flow of the β‐AuGa phase was observed which deteriorated the interface uniformity, causing an increase in contact resistance. A typical contact edge slide distance after contact alloying at 440 °C for 2 min was measured to be 0.2 μm and the longest distance among specimens examined was 0.47 μm. This edge deterioration could limit the use of the AuNiGe contact in GaAs submicron devices.

A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates

Threshold voltage (V_t) of a field effect transistor (FET) is observed to shift with stressing time and this stress induced V _t shift is an important transistor reliability issue. V_t shifts that occur under negative gate bias is referred as NBTI and those that occur under positive bias is referred as PBTI or charge trapping. In this paper, we present a comparative study of NBTI and PBTI for a variety of FETs with different dielectric stacks and gate materials. The study has two parts. In part I, NBTI and PBTI measurements are performed for FUSI NiSi gated FETs with SiO₂ SiO₂/HfO₂ and SiO₂/HfSiO as gate dielectric stacks and the results are compared with those for conventional SiON/poly-Si FETs. The main results are: (i) NBTI for SiO ₂/NiSi and SiO₂/HfO₂/NiSi are same as those conventional SiON/poly-Si FETs; (ii) PBTI significantly increases as the Hf content in the high K layer is increased; and (iii) PBTI is a greater reliability issue than NBTI for HfO₂/NiSi FETs. In part II of the study, NBTI and PBTI measurements are performed for SiO2/HfO2 devices with TiN and Re as gates and the results are compared with those for NiSi gated FETs. The main results are: (i) NBTI for SiO ₂/HfO₂/TiN and SiO₂/HfO₂/Re pFETs are similar with those observed for NiSi gated pFETs; and (ii) PBTI in TiN and Re gated HfO₂ devices is much smaller than those observed for SiO₂/HfO₂/NiSi. In summary for SiO₂/HfO₂ stacks, NBTI is observed to be independent of gate material whereas PBTI is significantly worse for FUSI gated devices. Consequently, HfO₂ FETs with TiN and Re gates exhibit over all superior transistor reliability characteristics in comparison to HfO₂/FUSI FETs

Unpinned gallium oxide/GaAs interface by hydrogen and nitrogen surface plasma treatment

The Fermi level at the Ga oxide/GaAs interface has been unpinned by rf plasma cleaning the GaAs surface in H2 and N2. Following plasma cleaning, a Ga oxide film is reactively electron beam deposited onto the substrate. Metal‐oxide‐semiconductor (MOS) capacitors fabricated on these structures show good high‐frequency capacitance‐voltage characteristics. This indicates that the density of interface states has been reduced to ∼1011 eV−1 cm−2. The MOS capacitors are found to be stable in air after several months.

Microstructure studies of AuNiGe Ohmic contacts to n‐type GaAs

Microstructure analysis and contact resistance measurements of alloyed AuNiGe contacts to GaAs were performed to assist in the development of low resistance Ohmic contacts for metal–semiconductor field‐effect transistor (MESFET) devices. The contact metals were prepared by sequential deposition of 100 nm of Au–27 at. % Ge, 35 nm Ni, and 50 nm Au onto sputter‐cleaned GaAs wafers in which conducting channels were formed by Si doping to a level of about 1×1018 cm−3. The contact resistances were determined by the transmission line method. Analysis of the substrate and the film microstructure was carried out by x‐ray diffraction, Auger electron spectroscopy (AES), and x‐ray photoelectron spectroscopy (XPS). A strong correlation between the contact resistance and the film microstructure was observed. Low resistances were observed when NiAs compounds containing Ge were in contact with GaAs and the β‐AuGa phase was concentrated near the top of the contact. High resistances were measured when free Au, the α‐AuGa p...

Inversion mode n-channel GaAs field effect transistor with high-k/metal gate

Highly effective passivation of GaAs surface is achieved by a thin amorphous Si (a-Si) cap, deposited by plasma enhanced chemical vapor deposition method. Capacitance voltage measurements show that carrier accumulation or inversion layer is readily formed in response to an applied electrical field when GaAs is passivated with a-Si. High performance inversion mode n-channel GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated with an a-Si/high-k/metal gate stack. Drain current in saturation region of 220mA∕mm with a mobility of 885cm2∕Vs were obtained at a gate overdrive voltage of 3.25V in MOSFETs with 5μm gate length.

Band-Edge High-Performance High-k/Metal Gate n-MOSFETs Using Cap Layers Containing Group IIA and IIIB Elements with Gate-First Processing for 45 nm and Beyond

We have fabricated electrically reliable band-edge (BE) high-k/metal nMOSFETs stable to 1000degC, that exhibit the highest mobility (203 cm2/Vs @ 1MV/cm) at the thinnest Tinv (1.4 nm) reported to date. These stacks are formed by capping HfO2 with ultra-thin layers containing strongly electropositive gp. IIA and IIIB elements (e.g. Mg and La), prior to deposition of the TiN/Poly-Si electrode stack, in a conventional gate-first flow. Increasing the cap thickness tunes the Vt/V fb from a midgap position to BE while maintaining high mobility and good PBTI. The addition of La can enhance the effective k value of the dielectric stack, resulting in EOTs < 1nm. Short channel devices with band edge characteristics are demonstrated down to 60 nm. Finally, possible mechanisms to explain the nFET Vt shift are discussed

Understanding mobility mechanisms in extremely scaled HfO 2 (EOT 0.42 nm) using remote interfacial layer scavenging technique and V t -tuning dipoles with gate-first process

We demonstrate a novel “remote interfacial layer (IL) scavenging” technique yielding a record-setting equivalent oxide thickness (EOT) of 0.42 nm using a HfO2-based MOSFET high-к gate dielectric. Intrinsic effects of IL scaling on carrier mobility are clarified using this method. We reveal that the mobility degradation observed for La-containing high-к is not due to the La dipole but due to the intrinsic IL scaling effect, whereas an Al dipole brings about additional mobility degradation. This unique nature of the La dipole enables aggressive EOT scaling in conjunction with IL scaling for the 16 nm technology node without extrinsic mobility degradation.

Improved process for high‐Tc superconducting step‐edge junctions

We have developed a process for the fabrication of YBaCuO high‐Tc junctions based on the step‐edge weak‐link concept. The process emphasizes the creation of sharp and straight step edges on a substrate, and the restoration of oxygen content for superconducting materials at the step edges. A diamond‐like carbon film is used as an ion milling mask for the creation of steps on substrates such as LaAlO3 and SrTiO3. Room‐temperature plasma oxidation is shown to be effective in restoring Tc from processing related degradation for grains residing at the step edge. Using this process, dc SQUIDs were fabricated with 77 K electrical performances matching, and in certain cases exceeding, similar SQUIDs made using bicrystal‐based tilt‐boundary weak‐link junctions.