R. B. Gregory

Effects of anneal ambients and Pt thickness on Pt/Ti and Pt/Ti/TiN interfacial reactions

Using x‐ray diffraction, Rutherford backscattering spectrometry, Auger electron spectroscopy, and scanning electron microscopy, effects of ambient anneal and Pt thickness on the interdiffusion of Pt/Ti bilayers deposited on SiO2/Si and on reactively sputtered TiN/Ti/Si substrates have been investigated. The Pt layer was 2000 or 930 A thick while the Ti thickness was fixed at 1000 A. The wafers were annealed in either O2 or N2 ambients or in N2 followed by O2, with temperatures ranging from 600 to 800 °C for 30 min. The anneal ambients and the thickness of Pt relative to the Ti layer had tremendous effects on the interdiffusion processes, the reaction products, and the surface morphology of the multilayer structures. Samples annealed in O2 were generally rough, with bumps of the order of 1000 A, while those annealed in N2 were relatively smooth. With lead zirconium titanate on top, the surface of Pt/Ti electrode annealed in O2 at 650 °C was relatively smooth.

Interdiffusions in Cu/reactive‐ion‐sputtered TiN, Cu/chemical‐vapor‐deposited TiN, Cu/TaN, and TaN/Cu/TaN thin‐film structures: Low temperature diffusion analyses

A comparative study of reactively‐ion‐sputtered (RIS) and low pressure chemical‐vapor‐deposited (LPCVD) TiN, and sputter‐deposited TaN thin films as diffusion barriers for Cu has been done using Auger electron spectroscopy, Rutherford backscattering spectrometry, x‐ray diffraction, scanning electron microscopy, and sheet resistance measurements. For the RIS TiN and sputtered TaN diffusion barriers, the integrity of the individual layers was preserved and there was no evidence of interdiffusion for samples annealed up to 500 °C in N2–H2 ambient for 1 hour. The LPCVD TiN was stable up to 450 °C for 30 minutes only, after which Cu started to diffuse into the TiN layer. The reasons for the higher thermal stability of RIS TiN compared to LPCVD TiN can be deduced from the microstructural differences in the two films, as observed with x‐ray diffraction technique.

Physical and electrical properties of metal gate electrodes on HfO2 gate dielectrics

As the metal–oxide–semiconductor field-effect transistor (MOSFET) gate lengths scale down to 50 nm and below, the expected increase in gate leakage will be countered by the use of a high dielectric constant (high-k) gate oxide. The series capacitance from polysilicon gate electrode depletion significantly reduces the gate capacitance as the dielectric thickness is scaled to 10 A equivalent oxide thickness (EOT) or below. Metal gates promise to solve this problem and address other gate stack scaling concerns like boron penetration and elevated gate resistance. Extensive simulations have shown that the optimal gate work functions for the sub-50 nm channel lengths should be 0.2 eV below (above) the conduction (valence) band edge of silicon for n-type MOSFETs (p-type MOSFETs). This study summarizes the evaluations of TiN, Ta–Si–N, WN, TaN, TaSi, Ir, and IrO2 as candidate metals for dual-metal gate complementary metal–oxide semiconductor using HfO2 as the gate dielectric. The gate work function was determined ...

Characterization of sputtered barium strontium titanate and strontium titanate-thin films

Sputtered Ba1−xSrxTiO3 (BST) and SrTiO3 (STO) films and capacitors made with these dielectrics have been characterized with respect to physical and electrical properties. Specific capacitance values included a high of 96 fF/μm2 for BST films deposited of 600 °C and a high of 26 fF/μm2 for STO films deposited at 400 °C. Leakage current densities at 3.3 V for the most part varied from mid 10−8 to mid 10−6 A/cm2. All of the dielectrics are polycrystalline, although the lowest temperature STO films have a nearly amorphous layer which impacts their capacitance. Grain size increases with deposition temperature, which correlates to higher dielectric constants. The lattice parameter of the BST films is larger than that of bulk samples. Capacitance, leakage, breakdown, and lifetime results are reported.

Optical properties of bulk and thin-film SrTiO3 on Si and Pt

We have studied the optical properties (complex dielectric function) of bulk SrTiO3 and thin films on Si and Pt using spectroscopic ellipsometry over a very broad spectral range, starting at 0.03 eV [using Fourier transform infrared (FTIR) ellipsometry] to 8.7 eV. In the bulk crystals, we analyze the interband transitions in the spectra to determine the critical-point parameters. To interpret these transitions, we performed band structure calculations based on ab initio pseudopotentials within the local-density approximation. The dielectric function was also calculated within this framework and compared with our ellipsometry data. In the FTIR ellipsometry data, we notice a strong lattice absorption peak due to oxygen-related vibrations. Two longitudinal optic (LO) phonons were also identified. In SrTiO3 films on Si, the refractive index below the band gap decreases with decreasing thickness because of the increasing influence of the amorphous interfacial layer between the SrTiO3 film and the Si substrate....

Rapid isothermal annealing of As-, P-, and B-implanted silicon

Single‐crystal silicon wafers have been implanted with As, P, and B to doses of 1×1013–1×1016/cm2 and given a transient anneal using a Varian IA‐200 Rapid Isothermal Annealer. The system uses infrared radiation to heat the wafers to temperatures in excess of 1000 °C for times on the order of 10 sec. Sheet resistance and Hall measurements have been used to determine the effect of the anneal on the electrical properties of the wafers. Rutherford backscattering and secondary ion mass spectroscopy have been used to measure lattice damage and dopant profiles before and after annealing. As and P are lost during the anneal unless the wafer is capped. Complete activation can be achieved with very little dopant diffusion. Residual damage is minimal in (100) oriented wafers that had been implanted with As. However, for (111) wafers damage is less in (111) wafers implanted to doses ≥5.0×1015/cm2, than in (111) wafers implanted to doses ≤5.0×1015/cm2. The diffusion of As during this transient anneal has been modeled ...

Characteristics of atomic-layer-deposited thin HfxZr1−xO2 gate dielectrics

In this study, the authors investigated the addition of zirconium (Zr) into HfO2 to improve its dielectric properties. HfxZr1−xO2 films were deposited by atomic-layer deposition at 200–350°C and annealed in a nitrogen ambient environment at 1000°C. Extensive physical characterization of the impact of alloying Zr into HfO2 is studied using vacuum ultraviolet spectroscopy ellipsometry, attenuated total reflectance Fourier transform infrared spectroscopy, secondary-ion mass spectrometry, transmission electron microscopy, atomic force microscopy, x-ray diffraction, Rutherford backscattering spectrometry, and x-ray reflectometry. HfxZr1−xO2 transistors are fabricated to characterize the impact of Zr addition on electrical thickness, mobility, and reliability. Zr addition into HfO2 leads to changes in film microstructure and grain-size distribution. HfxZr1−xO2 films have smaller and more uniform grain size compared to HfO2 for all deposition temperatures explored here. As Zr content and deposition temperature a...

Role of Ga2O3 template thickness and gadolinium mole fraction in GdxGa0.4−xO0.6/Ga2O3 gate dielectric stacks on GaAs

Amorphous GdxGa0.4−xO0.6/Ga2O3 gate dielectric stacks have been grown onto the GaAs(001) surface by molecular beam epitaxy using high temperature effusion cells. The Ga2O3 template thickness and the Gd mole percent have been systematically varied from 73 to 0 A and from 8.8 to 22 at. % (0.088⩽x⩽0.22), respectively. Oxide/n-type GaAs samples have been characterized by high-frequency capacitance–voltage measurements. Optimum gate oxide stack and oxide/GaAs interface properties are obtained with a Ga2O3 template thickness of 9–11 A and a minimum Gd mole percent of 15–17 at. %. While gate oxide films with thicker Ga2O3 templates and/or lower Gd mole fraction show kinks in capacitance–voltage measurements attributed to charge trapping in the oxide, thinner Ga2O3 templates lead to strong stretch-out of capacitance–voltage curves indicating severely degraded oxide/GaAs interface properties.

Auger electron spectroscopy and Rutherford backscattering characterization of TiNx/TiSiy contact barrier metallization

We have studied both the formation and integrity of TiNx/TiSiy bilayer films formed by reacting sputter deposited Ti films on Si substrates in nitrogen containing ambients. Auger electron spectroscopy and Rutherford backscattering spectrometry have been used to characterize the formation and properties of these bilayer films as a function of the ambient composition, the substrate doping, and the method of heating [furnace or rapid thermal annealing (RTA)]. We have also characterized the B and As substrate dopant redistribution which occurs during the bilayer formation. Barrier integrity was measured by depositing 2 kA of Al–Si(1%)–Cu(1%) on top of the TiNx/TiSiy bilayers and thermally stressing the films at 450 °C for times ranging from 0.5 to 6.0 h. The metallurgical breakdown of the Al/barrier/Si was characterized by Auger depth profiling and the integrity of the barriers was correlated with the various parameters of the barrier formation. It is concluded that the properties of the nitride/silicide bila...

Grain growth during transient annealing of As‐implanted polycrystalline silicon films

Polycrystalline silicon films deposited on oxidized wafer surfaces were implanted with As and annealed on a Varian IA‐200 rapid thermal annealer. The effects of annealing conditions on resultant grain size of original as‐deposited columnar grains are presented with a modified model for interfacially driven grain growth. During an initial temperature rise to 910 °C the original grain size (39 nm) and dopant profile are not significantly altered. At 1145 °C the grains have grown to 90 nm and the As is uniformly distributed throughout the film. Additional annealing to 1300 °C in 20 s causes grains to grow to 260 nm. Further grain growth is retarded due to the 300‐nm film thickness. During annealing of unencapsulated films a substantial loss of As results in a lower rate of grain growth. When grain size increases, Hall mobility increases and resistivity decreases.