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A hierarchical vision processing architecture oriented to 3D integration of smart camera chips

This paper introduces a vision processing architecture that is directly mappable on a 3D chip integration technology. Due to the aggregated nature of the information contained in the visual stimulus, adapted architectures are more efficient than conventional processing schemes. Given the relatively minor importance of the value of an isolated pixel, converting every one of them to digital prior to any processing is inefficient. Instead of this, our system relies on focal-plane image filtering and key point detection for feature extraction. The originally large amount of data representing the image is now reduced to a smaller number of abstracted entities, simplifying the operation of the subsequent digital processor. There are certain limitations to the implementation of such hierarchical scheme. The incorporation of processing elements close to the photo-sensing devices in a planar technology has a negative influence in the fill factor, pixel pitch and image size. It therefore affects the sensitivity and spatial resolution of the image sensor. A fundamental tradeoff needs to be solved. The larger the amount of processing conveyed to the sensor plane, the larger the pixel pitch. On the contrary, using a smaller pixel pitch sends more processing circuitry to the periphery of the sensor and tightens the data bottleneck between the sensor plane and the memory plane. 3D integration technologies with a high density of through-silicon-vias can help overcome these limitations. Vertical integration of the sensor plane and the processing and memory planes with a fully parallel connection eliminates data bottlenecks without compromising fill factor and pixel pitch. A case study is presented: a smart vision chip designed on a 3D integration technology provided by MIT Lincoln Labs, whose base process is 0.15@mm FD-SOI. Simulation results advance performance improvements with respect to the state-of-the-art in smart vision chips.

Realization of non-linear templates using the CNNUC3 prototype

Demonstrates the processing capabilities of an analog programmable array processor chipMINUS/CNNUC3-which follows the cellular neural network Universal Machine computing paradigm. Due to its very advanced features and algorithmic capabilities, this chip has been demonstrated to be able to perform not only linear templates executions, but also to be very adequate for the implementation of non-linear templates by using a decomposition method. The paper focuses on the application examples of the execution of non-linear templates with the CNNUC3 prototype. A brief description of the theoretical background is also presented in the paper.

Displacement calculation algorithm on a heterogenious multi-layer cellular sensor processor array

Displacement calculation algorithm is implemented on a heterogeneous sensor processor architecture, constructed of a mixed signal medium resolution processor array, and a digital, low resolution, foveal processor array. The algorithm is designed as an initial step of an airborne navigation framework. It features multi-scale multi-fovea processing.

Structure reconfigurability of the CNNUC3 for robust template operation

We demonstrate the importance of the reconfigurability of a 64/spl times/64 cells size CNN-UM chip. As we show, in such a high complexity mixed-signal VLSI circuit the switch and internal reference level reconfigurability and reprogrammability play a crucial role for the robust operation of the system. The methodology for exploring the possibilities is three-fold, we consider theoretical results, error compensation methods, and the usage of special features of the design.

A behavioural modelling technique for visual microprocessor mixed-signal VLSI chips

Contract/grant sponsor: ONR-NICOP; contract/grant number: N68171-98-C-9004. Contract/grant sponsor: DICTAM; contract/grant number: IST-1999-19007. Contract/grant sponsor: TIC; contract/grant number: 990826.

Object oriented image segmentation on the CNNUC3 chip

We show how a complex object oriented image analysis algorithm can be implemented on a CNNUM chip for video-coding. Besides the applied linear operations, several gray-scale nonlinear template operations are also emulated using algorithmic solutions.

Implementation of non-linear templates using a decomposition technique by a 0.5 /spl mu/m CMOS CNN universal chip

This paper demonstrates the processing capabilities of a recently designed analog programmable array processor. This new prototype, called CNNUC3, follows the cellular neural network universal machine computing paradigm. Due to its very advanced features and algorithmic capabilities, this chip has been demonstrated to be able to perform not only linear templates executions, but also to be very adequate for the implementation of non-linear templates by using a decomposition method. This paper focus on the application examples of the execution of non-linear templates with the CNNUC3 prototype. A brief description of the theoretical background is also presented in the paper.