S. Espejo

Current-mode techniques for the implementation of continuous- and discrete-time cellular neural networks

A unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) cellular neural networks (CNNs) using CMOS current-mode analog techniques is presented. The net input signals are currents instead of voltages, which avoids the need for current-to-voltage dedicated interfaces in image processing tasks with photosensor devices. Outputs may be either currents or voltages. Cell design relies on exploiting current mirror properties for the efficient implementation of both linear and nonlinear analog operators. Basic design issues, the influence of nonidealities and advanced circuit design issues, and design for manufacturability considerations associated with statistical analysis are discussed. Experimental results are given for three prototypes designed for 1.6- mu m n-well CMOS technologies. One is discrete-time and can be reconfigured via local logic for noise removal, feature extraction (borders and edges), shadow detection, hole filling, and connected component detection (CCD) on a rectangular grid with unity neighborhood radius. The other two prototypes are continuous-time and fixed template: one for CCD and other for noise removal. >

A CNN universal chip in CMOS technology

This paper describes the design of a programmable cellular neural network (CNN) chip with added functionalities similar to those of the CNN universal machine. The prototype contains 1024 cells and has been designed in a 1.0 μm, n-well CMOS technology. Careful selection of the topology and design parameters has resulted in a cell density of 31 cells mm -2 and around 7-8 bits accuracy in the weight values. Adaptive techniques have been employed to ensure accurate external control and system robustness against process parameter variations.

A VLSI‐oriented continuous‐time CNN model

This paper presents an analysis of the stability and convergence properties of the full signal range (FSR) CNN model. These properties are demonstrated to be similar to those of the Chua-Yang model and the I/O mapping of known applications is shown to be unaffected by the modification introduced in this new model. In this modified CNN model the dynamic range of the cell state variables equals the dynamic range of the cell output variables and is invariant with the application. This feature results in simpler circuit implementations, thus allowing higher cell densities and improving the robustness of CNN integrated circuits. The FSR CNN model is particularly well suited for programmable CNN integrated circuits.

A 1000 FPS at 128/spl times/128 vision processor with 8-bit digitized I/O

This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of processing elements, arranged to operate in accordance with the principles of single instruction multiple data (SIMD) computing architectures. This chip, implemented in a 0.35-/spl mu/m fully digital CMOS technology, contains /spl sim/ 3.75 M transistors and exhibits peak performance figures of 330 GOPS (8-bit equivalent giga-operations per second), 3.6 GOPS/mm/sup 2/ and 82.5 GOPS/W. It includes structures for image acquisition and for image processing, meaning that it does not require a separate imager for operation. At the sensory side, integration and log-compression sensing circuits are embedded, thus allowing the chip to handle a large variety of illumination conditions. At the processing plane, analog and digital circuits are employed whose parameters can be programmed and their architecture reconfigured for the realization of software-coded processing algorithms. The chip provides, and accepts, 8-bit digitized data through a 32-bit bidirectional data bus which operates at 120 MB/s. Experimental results show that frame rates of 1000 frames per second (FPS) can be achieved under room illumination conditions; applications using exposures of about 50 /spl mu/s have been recently reached by using special illumination setups. The chip can capture an image, run approximately 150 two-dimensional linear convolutions, and download the result in 8-bit digital format, in less than 1 ms. This feature, together with the possibility of executing sequences of user-definable instructions (stored on a full-custom 32-kb on-chip memory), and storing intermediate results (up to 8 grayscale images) makes the chip a true general-purpose sensory/processing device.

ACE4k: An analog I/O 64×64 visual microprocessor chip with 7-bit analog accuracy

Funded by: ONR-NICOP. Grant Number: N68171-98-C-9004; DICTAM. Grant Number: IST-1999-19007 and CICYT TIC. Grant Number: 1999 0826.

Smart-pixel cellular neural networks in analog current-mode CMOS technology

This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capabilities. These chips consist of regular arrangements of elementary units, called smart pixels. Light detection is made with vertical CMOS-BJTs connected in a Darlington structure. Pixel smartness is achieved by exploiting the cellular neural network paradigm, incorporating at each pixel location an analog computing cell which interacts with those of nearby pixels. We propose a current-mode implementation technique and give measurements from two 16 x 16 prototypes in a single-poly double-metal CMOS n-well 1.6-/spl mu/m technology. In addition to the sensory and processing circuitry, both chips incorporate light-adaptation circuitry for automatic contrast adjustment. They obtain smart-pixel densities up to 89 units/mm/sup 2/, with a power consumption down to 105 /spl mu/W/unit and image processing times below 2 /spl mu/s. >

A 64/spl times/64 CNN universal chip with analog and digital I/O

This paper describes general characteristics of a 64/spl times/64 cells CNN universal chip with enhanced functionality as compared to previous releases. The prototype is a true mixed-signal ASIC and has been designed in CMOS 0.5 /spl mu/m technology. It is conceived to be the core component of a new class of video-processing systems for advanced multimedia applications.

The Eye-RIS CMOS Vision System

Eye-RIS is the name of a family of vision systems which are conceived for single-chip integration using CMOS technologies. The Eye-RIS systems employ a bio-inspired architecture where image acquisition and processing are truly intermingled and the processing itself is realized in two steps. At the first step processing is fully parallel owing to the concourse of dedicated circuit structures which are integrated close to the sensors. These circuit structures handle basically analog information. At the second step, processing is realized on digitally-coded information data by means of digital processors. Overall, the processing architecture resembles that of natural vision systems, where parallel processing is made at the retina (first layer) and significant reduction of the information happens as the signal travels from the retina up to the visual cortex. This chapter outlines the concept of the Eye-RIS system and its main components and presents experimental data to illustrate its practical operation.

A bio-inspired two-layer mixed-signal flexible programmable chip for early vision

A bio-inspired model for an analog programmable array processor (APAP), based on studies on the vertebrate retina, has permitted the realization of complex programmable spatio-temporal dynamics in VLSI. This model mimics the way in which images are processed in the visual pathway, what renders a feasible alternative for the implementation of early vision tasks in standard technologies. A prototype chip has been designed and fabricated in 0.5 /spl mu/m CMOS. It renders a computing power per silicon area and power consumption that is amongst the highest reported for a single chip. The details of the bio-inspired network model, the analog building block design challenges and trade-offs and some functional tests results are presented in this paper.

Ultra-high frame rate focal plane image sensor and processor

Application examples of a fully-programmable analogic focal plane array processor are introduced. One mixed-signal sensory/processing chip is presented, which is capable of capturing, processing, and evaluating over 10,000 images in a second. Morphological analysis of silhouettes and sparks were carried out and real-time decision making was performed running at this extraordinary high frame-rate.