R. Dominguez-Castro

Nonlinear switched capacitor 'neural' networks for optimization problems

A systematic approach is presented for the design of analog neural nonlinear programming solvers using switched-capacitor (SC) integrated circuit techniques. The method is based on formulating a dynamic gradient system whose state evolves in time toward the solution point of the corresponding programming problem. A neuron cell for the linear and the quadratic problem suitable for monolithic implementation is introduced. The design of this neuron and its corresponding synapses using SC techniques is considered in detail. An SC circuit architecture based on a reduced set of basic building blocks with high modularity is presented. Simulation results using a mixed-mode simulator (DIANA) and experimental results from breadboard prototypes are included, illustrating the validity of the proposed techniques. >

ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs

Today, with 0.18-/spl mu/m technologies mature and stable enough for mixed-signal design with a large variety of CMOS compatible optical sensors available and with 0.09-/spl mu/m technologies knocking at the door of designers, we can face the design of integrated systems, instead of just integrated circuits. In fact, significant progress has been made in the last few years toward the realization of vision systems on chips (VSoCs). Such VSoCs are eventually targeted to integrate within a semiconductor substrate the functions of optical sensing, image processing in space and time, high-level processing, and the control of actuators. The consecutive generations of ACE chips define a roadmap toward flexible VSoCs. These chips consist of arrays of mixed-signal processing elements (PEs) which operate in accordance with single instruction multiple data (SIMD) computing architectures and exhibit the functional features of CNN Universal Machines. They have been conceived to cover the early stages of the visual processing path in a fully-parallel manner, and hence more efficiently than DSP-based systems. Across the different generations, different improvements and modifications have been made looking to converge with the newest discoveries of neurobiologists regarding the behavior of natural retinas. This paper presents considerations pertaining to the design of a member of the third generation of ACE chips, namely to the so-called ACE16k chip. This chip, designed in a 0.35-/spl mu/m standard CMOS technology, contains about 3.75 million transistors and exhibits peak computing figures of 330 GOPS, 3.6 GOPS/mm/sup 2/ and 82.5 GOPS/W. Each PE in the array contains a reconfigurable computing kernel capable of calculating linear convolutions on 3/spl times/3 neighborhoods in less than 1.5 /spl mu/s, imagewise Boolean combinations in less than 200 ns, imagewise arithmetic operations in about 5 /spl mu/s, and CNN-like temporal evolutions with a time constant of about 0.5 /spl mu/s. Unfortunately, the many ideas underlying the design of this chip cannot be covered in a single paper; hence, this paper is focused on, first, placing the ACE16k in the ACE chip roadmap and, then, discussing the most significant modifications of ACE16K versus its predecessors in the family.

A 0.8-/spl mu/m CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage

This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) binary images. Its processing function is determined by a reduced set of 19 analog coefficients whose values are programmable with 7-b accuracy. The internal programming signals are analog, but the external control interface is fully digital. On-chip nonlinear digital-to-analog converters (DACs) map digitally coded weight values into analog control signals, using feedback to predistort their transfer characteristics in accordance to the response of the analog programming circuitry. This strategy cancels out the nonlinear dependence of the analog circuitry with the programming signal and reduces the influence of interchip technological parameters random fluctuations. The chip includes a small digital RAM memory to store eight sets of processing parameters in the periphery of the cell array and four 2-D binary images spatially distributed over the processing array. It also includes the necessary control circuitry to realize the stored instructions in any order and also to realize programmable logic operations among images. The chip architecture is based on the cellular neural/nonlinear network universal machine (CNN-UM). It has been fabricated in a 0.8-/spl mu/m single-poly double-metal technology and features 2-/spl mu/s operation speed (time required to process an image) and around 7-b accuracy in the analog processing operations.

A CNN universal chip in CMOS technology

This paper describes the design of a programmable cellular neural network (CNN) chip with added functionalities similar to those of the CNN universal machine. The prototype contains 1024 cells and has been designed in a 1.0 μm, n-well CMOS technology. Careful selection of the topology and design parameters has resulted in a cell density of 31 cells mm -2 and around 7-8 bits accuracy in the weight values. Adaptive techniques have been employed to ensure accurate external control and system robustness against process parameter variations.

A VLSI‐oriented continuous‐time CNN model

This paper presents an analysis of the stability and convergence properties of the full signal range (FSR) CNN model. These properties are demonstrated to be similar to those of the Chua-Yang model and the I/O mapping of known applications is shown to be unaffected by the modification introduced in this new model. In this modified CNN model the dynamic range of the cell state variables equals the dynamic range of the cell output variables and is invariant with the application. This feature results in simpler circuit implementations, thus allowing higher cell densities and improving the robustness of CNN integrated circuits. The FSR CNN model is particularly well suited for programmable CNN integrated circuits.

A statistical optimization-based approach for automated sizing of analog cells

This paper presents a CAD tool for automated sizing of analog cells using statistical optimization in a simulation based approach. A nonlinear penalty-like approach is proposed to define a cost function from the performance specifications. Also, a group of heuristics is proposed to increase the probability of reaching the global minimum as well as to reduce CPU time during the optimization process. The proposed tool sizes complex analog cells starting from scratch, within reasonable CPU times (approximately 1 hour for a fully differential opamp with 51 transistors), requiring no designer interaction, and using accurate transistor models to support the design choices. Tool operation and feasibility is demonstrated via experimental measurements from a working CMOS prototype of a folded-cascode amplifier.

High resolution CMOS current comparators: design and applications to current-mode function generation

This paper uses fundamental models to derive design conditions for maximum speed and resolution in CMOS transimpedance comparators. We distinguish two basic comparator architectures depending on whether the input sensing node is resistive or capacitive, and show that each type yields advantages for different ranges of input current. Then, we introduce a class of current comparator structures which use nonlinear sensing and/or feedback to combine the advantages of capacitive-input and resistive-input architectures. Two members of this class are presented demonstrating resolution levels (measured on silicon prototypes) in the range of pAs. They exhibit complementary functional features: one, the current steering comparator, displays better transient response in the very comparison function, while operation of the other, the current switch comparator, is easily extended to support systematic generation of nonlinear transfer functions in current domain. The paper explores also this latter extension, and presents current-mode circuit blocks for systematic generation of nonlinear functions based on piecewise-linear (PWL) approximation. Proposals made in the paper are demonstrated via CMOS prototypes in two single-poly CMOS n-well technologies: 2μm and 1.6μm. These prototypes show measured input current comparison range of 140 dB, resolution and offset below 10 pA, and operation speed two orders of magnitude better than that of conventional resistive-input circuits. Also, measurements from the PWL prototypes show excellent rectification properties (down to a few pAs) and small linearity errors (down to 0.13%).

A 1000 FPS at 128/spl times/128 vision processor with 8-bit digitized I/O

This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of processing elements, arranged to operate in accordance with the principles of single instruction multiple data (SIMD) computing architectures. This chip, implemented in a 0.35-/spl mu/m fully digital CMOS technology, contains /spl sim/ 3.75 M transistors and exhibits peak performance figures of 330 GOPS (8-bit equivalent giga-operations per second), 3.6 GOPS/mm/sup 2/ and 82.5 GOPS/W. It includes structures for image acquisition and for image processing, meaning that it does not require a separate imager for operation. At the sensory side, integration and log-compression sensing circuits are embedded, thus allowing the chip to handle a large variety of illumination conditions. At the processing plane, analog and digital circuits are employed whose parameters can be programmed and their architecture reconfigured for the realization of software-coded processing algorithms. The chip provides, and accepts, 8-bit digitized data through a 32-bit bidirectional data bus which operates at 120 MB/s. Experimental results show that frame rates of 1000 frames per second (FPS) can be achieved under room illumination conditions; applications using exposures of about 50 /spl mu/s have been recently reached by using special illumination setups. The chip can capture an image, run approximately 150 two-dimensional linear convolutions, and download the result in 8-bit digital format, in less than 1 ms. This feature, together with the possibility of executing sequences of user-definable instructions (stored on a full-custom 32-kb on-chip memory), and storing intermediate results (up to 8 grayscale images) makes the chip a true general-purpose sensory/processing device.

ACE4k: An analog I/O 64×64 visual microprocessor chip with 7-bit analog accuracy

Funded by: ONR-NICOP. Grant Number: N68171-98-C-9004; DICTAM. Grant Number: IST-1999-19007 and CICYT TIC. Grant Number: 1999 0826.

Smart-pixel cellular neural networks in analog current-mode CMOS technology

This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capabilities. These chips consist of regular arrangements of elementary units, called smart pixels. Light detection is made with vertical CMOS-BJTs connected in a Darlington structure. Pixel smartness is achieved by exploiting the cellular neural network paradigm, incorporating at each pixel location an analog computing cell which interacts with those of nearby pixels. We propose a current-mode implementation technique and give measurements from two 16 x 16 prototypes in a single-poly double-metal CMOS n-well 1.6-/spl mu/m technology. In addition to the sensory and processing circuitry, both chips incorporate light-adaptation circuitry for automatic contrast adjustment. They obtain smart-pixel densities up to 89 units/mm/sup 2/, with a power consumption down to 105 /spl mu/W/unit and image processing times below 2 /spl mu/s. >