Peter H. Alfke

A high I/O reconfigurable crossbar switch

A crossbar switch with 928 inputs and 928 outputs is presented. Switching elements are constructed using logic in the routing fabric. This approach yields a 16/spl times/ improvement in logic density compared with using conventional logic. Normally, the routing is fixed. However, in FPGAs (field programmable gate arrays), the interconnection is defined by the state of SRAM configuration cells, which are dynamically modifiable. Therefore, the switch is implemented on an FPGA using partial configuration to modify routing resources during operation. All paths are synchronously clocked at 155.5 MHz, creating a total throughput of 144.3 Gbits/s. to maintain constant clock latency across all paths, partially configurable delay registers are used. Finally, the partial reconfiguration controller is implemented in hardware to enable fast switch updates.

The next generation 65-nm FPGA

This article consists of a collection of slides from the authors conference presentation on Xilinxs Virtex-5 family of 65-nm FPGA products. Some of the specific topics discussed include: a description of Virtex special features, system specifications, and technology innovations; improved I/O performance; benchmarking Virtex-5, LUT6 systems; the new Microblaze features in Virtex-5; and new areas of technological development.

Virtex-6 and Spartan-6, plus a look into the future

Recently, Xilinx introduced two new FPGA families, Virtex-6 and Spartan-6, closely related in architecture, but each optimized for different markets and applications: Virtex-6 for high performance, features and capacity; Spartan-6 for low cost and low power consumption. Both families take advantage of 40/45 nm technology, and both are derived from the successful Virtex-5 architecture. I will give an overview of the salient features and capabilities of both families. Then I will give a peek into the future, explaining the impact of rapidly rising development costs for all future technology nodes. That limits ASICs and ASSPs to serve only high-volume opportunities, and offers unique advantages for FPGAs. But we must overcome certain technical difficulties, and streamline the users design process.

20 years of FPGA evolution from glue logic to major system component

This article consists of a collection of slides from the authors conference presentation on he development, growth and future of field programmable gate arrays (FPGA), 1965 - 1985. Some of the specific topics discussed include: FPGA growth and Moores Law; the evolution of small-scale integration to medium-scale integration to large-scale integration evolving from bipolar to CMOS technology; the evolution of FPGA logic; and new areas of FPGA technological development.

Tutorial: 65 NM FPGAs, A Look Under the Hood Technology, Features, and Applications

Summary form only given. This tutorial describes the why and how of the new 65-nm families of Virtex-5 FPGAs. It describes several aspects of the technology that affect speed, density, and power consumption. The basic device structure and package design have a strong impact on pc-board signal integrity and supply decoupling requirements. Various new or improved features create opportunities for novel applications in digital signal processing, communications, computing and instrumentation.