Delon Levi

XBI: a Java-based interface to FPGA hardware

XBI(tm), the Xilinx Bitstream Interface is a set of Java (tm) classes which provide an Application Program Interface (API) into the Xilinx FPGA bitstream. This interface operates on either bitstreams generated by Xilinx design tools, or on bitstreams read back from actual hardware. This provides the capability of designing, modifying and dynamically modifying circuits in Xilinx XC4000 (tm) series FPGA devices. The programming model used by XBI is a 2D array of Configurable Logic Blocks (CLBs). Each CLB is referenced by a row and column, and all configurable resources in the selected CLB may be set or probed. Additionally, control of all routing resources adjacent to the selected CLB are made available. Because the code is written in Java, compilation times are very fast, and because control is at the CLB level, bitstreams can typically be modified or generated in times on the order of one second or less. This API has been used to construct complete circuits and to modify existing circuits. In addition, the object oriented support in the Java programming language has permitted a small library of parameterizable, object oriented macro circuits or Cores to be implemented. Finally, this API may be used as a base to construct other tools. This includes traditional design tools for performing tasks such as circuit placement and routing, as well as application specific tools to perform more narrowly defined tasks.

Run-Time Parameterizable Cores

As FPGAs have increased in density, the demand for predefined intellectual property has risen. Rather than re-invent commonly used circuitry, libraries of standard parts have become available from a variety of sources. Currently, all of these offerings are based on the standard ASIC design flow and are used to produce fixed designs. This paper discusses Run-Time Parameterizable or RTP Cores which are an extension of the traditional static core model. Written in the Java (tm) programming language, RTP Cores are created at run-time and may be used to dynamically modify existing circuitry. In addition to providing support for run-time reconfigurable computing, RTP Cores permit run-time parameterization of designs. This adds flexibility and portablilty unavailable in existing design environments.

Networking on chip with platform FPGAs

This paper is concerned with networking at the chip level. Networks on chip have become a convenient focus for discussing the architecture of systems on chip, and design methodologies for such systems. One central question for such a focus concerns the extent to which it is useful or realistic just to scale down approaches used conventionally in larger-area computer networking. Here, we discuss this question, in the context of the modern Platform FPGA device as a system on chip substrate. We illustrate the discussion with two design examples of networking on chip being implemented in an unconventional way.

A high I/O reconfigurable crossbar switch

A crossbar switch with 928 inputs and 928 outputs is presented. Switching elements are constructed using logic in the routing fabric. This approach yields a 16/spl times/ improvement in logic density compared with using conventional logic. Normally, the routing is fixed. However, in FPGAs (field programmable gate arrays), the interconnection is defined by the state of SRAM configuration cells, which are dynamically modifiable. Therefore, the switch is implemented on an FPGA using partial configuration to modify routing resources during operation. All paths are synchronously clocked at 155.5 MHz, creating a total throughput of 144.3 Gbits/s. to maintain constant clock latency across all paths, partially configurable delay registers are used. Finally, the partial reconfiguration controller is implemented in hardware to enable fast switch updates.

GeneticFPGA: evolving stable circuits on mainstream FPGA devices

GeneticFPGA is a Java-based tool for evolving digital circuits on Xilinx XC4000EX/sup TM/ and XC4000XL/sup TM/ devices. Unlike other FPGA architectures popular with evolutionary hardware researchers, the XC4000 series architectures cannot accept arbitrary configuration data. Only a small subset of configuration bit patterns will produce operational circuits; other configuration bit patterns produce circuits which are unreliable and may even permanently damage the FPGA device. GeneticFPGA uses novel software techniques to produce legal circuit configurations for these devices, permitting experimentation with evolvable hardware on the larger, faster more mainstream devices. In addition, these techniques have led to methods for evolving circuits which are neither temperature, voltage, nor silicon dependent. An 8-bit counter and several digital frequency dividers have been successfully evolved using this approach. GeneticFPGA uses Xilinxs JBits/sup TM/ interface to control the generation of bitstream configuration data and the XHWIF portable hardware interface to communicate with a variety of commercially available FPGA-based hardware. GeneticFPGA, JBits, and XHWIF are currently being ported to the Xilinx Virtex/sup TM/ family of devices, which will provide greatly increased reconfiguration speed and circuit density.

A Reconfigurable Content Addressable Memory

Content Addressable Memories or CAMs are popular parallel matching circuits. They provide the capability, in hardware, to search a table of data for a matching entry. This functionality is a high performance alternative to popular software-based searching schemes. CAMs are typically found in embedded circuitry where fast matching is essential. This paper presents a novel approach to CAM implementation using FPGAs and run-time reconfiguration. This approach produces CAM circuits that are smaller, faster and more flexible than traditional approaches.

HereBoy: a fast evolutionary algorithm

HereBoy is an evolutionary algorithm that combines features from genetic algorithms and simulated annealing, and also adds a new methodology for exploring the search space. It is particularly well suited for exploring large spaces, like those associated with evolvable hardware, although it can be applied to a wide range of search/optimization problems. Experimental data consistently shows that when compared to both genetic algorithms and simulated annealing, HereBoy requires up to 100X fewer iterations than a genetic algorithm and up to 10X fewer iterations than simulated annealing. In some cases HereBoy is able to solve problems to a degree of accuracy that a generic algorithm is unable to achieve. HereBoy also scales from small problems to larger problems significantly better than the other two algorithms.

Debug of reconfigurable systems

While FPGA design tools have progressed steadily, availability of tools to aid in debug of FPGA-based systems has lagged. In particular, support for debug of run-time reconfigurable (RTR) systems have been all but absent. In this paper we describe DDTScript, a scripting language to aid in design, debug and test of RTR systems. The DDTScript language is fully integrated with the BoardScope graphical debug tool and permits parameterization, instantiation, and removal of Run-time Parameterizable (RTP) Cores and other configurable circuit components. DDTScript also provides control of system level resources and supplies access to device state and configuration data. DDTScript is currently used not only to test and debug RTP Cores, but to construct and interact with complete designs. DDTScript is currently part of the JBits tool suite and supports the Xilinx Virtex family of FPGA devices.

GeneticFPGA: a java-based tool for evolving stable circuits

GeneticFPGA is a Java-based tool for evolving digital circuits on Xilinx XC4000EXTM and XC4000XLTM devices. Unlike other FPGA architectures popular with Evolutionary Hardware researchers, the XC4000 series architectures cannot accept arbitrary configuration data. Only a small subset of configuration bit patterns will produce operational circuits; other configuration bit patterns produce circuits which are unreliable and may even permanently damage the FPGA device. GeneticFPGA uses novel software techniques to produce legal circuit configurations for these devices, permitting experimentation with evolvable hardware on the larger, faster, more mainstream devices. In addition, these techniques have led to methods for evolving circuits which are neither temperature, voltage, nor silicon dependent. An 8-bit counter and several digital frequency dividers have been successfully evolved using this approach. GeneticFPGA uses Xilinxs JBitsTM interface to control the generation of bitstream configuration data and the XHWIF portable hardware interface to communicate with a variety of commercially available FPGA-based hardware. GeneticFPGA, JBits, and XHWIF are currently being ported to the Xilinx VirtexTM family of devices, which will provide greatly increased reconfiguration speed and circuit density.

Design advantages of run-time reconfiguration

FPGAs have been successfully used to accelerate a wide variety of applications on a large number of systems. The FPGA devices in these systems are typically configured once by the application and seldom perform any sort of reconfiguration during execution. With the advent of new device architectures and new software tools, the interest in Run-Time Reconfiguration or RTR has increased. As with previous efforts, the focus of RTR has primarily been either in purely theoretical work or in demonstrating performance improvements over software-based solutions. In this paper we explore some of the more practical design issues surrounding RTR systems, and evaluate the advantages of RTR in terms of savings in hardware and software complexity. Preliminary results indicate that RTR can dramatically reduce the amount of FPGA logic and software support necessary for even simple coprocessing applications.