Brandon J. Blodget

Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs

The paper describes architectural enhancements to Xilinx FPGAs that provide better support for the creation of dynamically reconfigurable designs. These are augmented by a new design methodology that uses pre-routed IP cores for communication between static and dynamic modules and permits static designs to route through regions otherwise reserved for dynamic modules. A new CAD tool flow to automate the methodology is also presented. The new tools initially target the Virtex-II, Virtex-II Pro and Virtex-4 families and are derived from Xilinxs commercial CAD tools

A Self-reconfiguring Platform

A self-reconfiguring platform is reported that enables an FPGA to dynamically reconfigure itself under the control of an embedded microprocessor. This platform has been implemented on Xilinx Virtex II tm and Virtex II Pro tm devices. The platform’s hardware architecture has been designed to be lightweight. Two APIs (Application Program Interface) are described which abstract the low level configuration interface. The Xilinx Partial Reconfiguration Toolkit (XPART), the higher level of the two APIs, provides methods for reading and modifying select FPGA resources. It also provides support for relocatable partial bitstreams. The presented self-reconfiguring platform enables embedded applications to take advantage of dynamic partial reconfiguration without requiring external circuitry.

A Lightweight Approach for Embedded Reconfiguration of FPGAs

This paper presents a lightweight approach for embedded reconfiguration of Xilinx Virtex II/spl trade/ series FPGAs. A hardware and software infrastructure is reported that enables an FPGA to dynamically reconfigure itself under the control of a soft microprocessor core that is instantiated on the same array. The system provides a highly integrated, lightweight approach to dynamic reconfiguration for embedded systems. It combines the benefits of intelligent control, fast reconfiguration and small overhead.

Modular partial reconfigurable in Virtex FPGAs

Modular systems implemented on Field-Programmable Gate Arrays can benefit from being able to load and unload modules at run-time, a concept that is of much interest in the research community. While dynamic partial reconfiguration is possible in Virtex series and Spartan series FPGAs, the configuration architecture of these devices is not amenable to modular reconfiguration, a limitation which has relegated research to theoretical or compromised resource allocation models. In this paper two methods for implementing modular dynamic reconfiguration in Virtex FPGAs are compared and contrasted. The first method offers simplicity and fast reconfiguration times, but limits the geometry and connectivity of the system. The second method, recently developed by the authors, enables modules to be allocated arbitrary areas of the FPGA, bridging the gap between theory and reality and unlocking the latent potential of partial reconfiguration. The later method has been demonstrated in three applications.

A high I/O reconfigurable crossbar switch

A crossbar switch with 928 inputs and 928 outputs is presented. Switching elements are constructed using logic in the routing fabric. This approach yields a 16/spl times/ improvement in logic density compared with using conventional logic. Normally, the routing is fixed. However, in FPGAs (field programmable gate arrays), the interconnection is defined by the state of SRAM configuration cells, which are dynamically modifiable. Therefore, the switch is implemented on an FPGA using partial configuration to modify routing resources during operation. All paths are synchronously clocked at 155.5 MHz, creating a total throughput of 144.3 Gbits/s. to maintain constant clock latency across all paths, partially configurable delay registers are used. Finally, the partial reconfiguration controller is implemented in hardware to enable fast switch updates.

A Virtual File System for Dynamically Reconfigurable FPGAs

Platform FPGAs have dramatically changed the role of FPGAs in embedded systems. With increased density and immersed complex IPs, FPGAs no longer simply play ‘a role’ in embedded systems – FPGAs are embedded systems. To accommodate the increased system capability of Platform FPGAs, they also host a rich embedded software environment. Embedded Linux has emerged as a common software infrastructure for embedded systems in general and is also being employed in FPGA-based embedded systems.

Adapting constant multipliers in a neural network implementation

The use of dynamic reconfiguration appears extremely attractive for implementing adaptive processing algorithms. Often, the adaption involves updating look-up tables based on a parameter which can only be determined at run-time. For reasons of efficiency, these look-up tables are read-only to the rest of the circuitry. This paper compares the use of run-time reconfiguration and read-only look-up tables, with a similar implementation using writable memories. The application under consideration is the multilayer perceptron neural network.

VirtexDS: a Virtex device simulator

Until recently FPGAs have been used almost exclusively to implement static circuits. Because FPGAs can be reprogrammed at any time, even in-system at run-time, interest in exploiting this mode of operation has steadily increased. One barrier to widespread use of Run-Time Reconfiguration (RTR) has been the lack of design tools. While tools such as JBits have begun to provide basic support for design entry, traditional verification tools such as simulators have been lacking. This paper discusses VirtexDS, a device level simulator for the Xilinx Virtex (tm) series. The approach taken by VirtexDS is to simulate at the device level, providing an interface which operates much like actual hardware. This approach not only supports simulation for run-time reconfiguration, but also interfaces easily to existing tools. In addition, this low-level simulation approach can provide higher performance than higher-level approaches to simulation.

Pre-route Assistant: A Routing Tool for Run-Time Reconfiguration

Pre-Route Assistant is a web utility that helps pre-route JBits [1] Run-Time Parameterizable Cores (RTPCores). Given the connection points, it produces the JBits calls to turn on the corresponding wires, that the user can cut and paste into their JBits code. Pre-Routed cores are useful for Run-Time Reconfigurable (RTR) applications, for they can be written directly to a device bitstream without additional routing overhead. Having a library of Parameterizable, Pre-Routed cores gives RTR applications much more flexibility and power. This paper introduces Pre-Route Assistant, explores why pre-routing is useful for RTR.

High-performance reconfigurable constant coefficient multiplier implementations

The use of dynamic reconfiguration appears extremely attractive for implementing adaptive processing algorithms. Often, the adaption involves updating look-up tables based on a parameter which can only be determined at run-time. For reasons of efficiency, these look-up tables are read-only to the rest of the circuitry. This paper compares the use of run-time reconfiguration and read-only look-up tables, with similar implementations using writable memories. The application under consideration is the multi-layer perceptron neural network. It is shown that the ROM based network is considerably simpler than the RAM based network, at the expense of a dramatically increased time to update the weights during training.