Peter Hsieh

Development of copper etch technology for advanced copper interconnects

Recent development efforts in copper etch processing show promising results in many areas that have posed significant challenges for this new technology. We report on the etch performance for features down to 0.25 /spl mu/m with aspect ratios greater than 2:1. Copper etch rates of over 5000 /spl Aring//min have been achieved, and corrosion-free post copper etch performance has been demonstrated for periods in excess of two weeks. Electrical and device yield tests were conducted and presented in detail.

Development of Cu etch process for advanced Cu interconnects

Recent development efforts in copper etch processing show promising results in many areas that have posed significant challenges for this new technology. We report on etch performance for features down to 0.25 /spl mu/m with aspect ratios greater than 2:1. Copper etch rates greater than 5000 /spl square//min have been achieved, and corrosion-free post Cu etch performance has been demonstrated for periods in excess of 72 hours. Electrical tests were conducted and are presented in detail.

The effect of interfacial oxide and high-κ thickness on NMOS V th shift from plasma-induced damage

Different thicknesses of interfacial oxide and high-κ were used to study the effects of plasma-induced damage (PID) in NMOS transistors. The thickness of high-κ HfO₂ was varied from 15Å to 25Å. The thickness of the interfacial layer (IL) with N₂O/H₂ was also varied from 5Å to 10Å. The threshold voltage (V_th) shift was observed to be greater in the thinner oxide using the same plasma condition. There was no significant effect with different IL thickness between 5Å and 10Å.