Petros Oikonomakos

Error correction in arithmetic operations by I/O inversion

In this paper we demonstrate how error-correcting addition and multiplication can be performed using self-checking modules. Our technique is based on the observation that a suitably designed full adder under the presence of any single stuck-at fault produces the fault-free complement of the desired output when fed by the complement of its functional input. We initially apply conventional parity-based error detection in arithmetic modules; upon detection of a fault, this is followed by input inversion, recomputation, and suitable output inversion. We present adder, register and multiplier designs that can be used in this context. We also design a large-scale circuit using this technique (an elliptical filter), outlining the area savings with respect to traditional triple modular redundancy

On the Design of Self-Checking Controllers with Datapath Interactions

We consider the problem of designing self-checking controllers for controller/datapath architectures. We introduce the concept of intrinsically secure states. We present six alternative schemes based on parity checking, on 1-out-of-n checking, as well as on the observation that a self-checking sequential datapath can also be employed for control path self-checking by exploiting the concept of intrinsically secure control states. A high-level synthesis tool has been modified to automatically insert self-checking controllers and datapath units and is able to trade this self-checking property against other design objectives. We discuss the properties of each configuration and present experimental results and conclusions

An Integrated High-Level On-Line Test Synthesis Tool

Several researchers have recently implemented on-line testability in the form of duplication-based self-checking digital system design, early in the design process. The authors consider the on-line testability within the optimization phase of iterative, cost function-driven high-level synthesis, such that self-checking resources are inserted automatically without any modification of the source behavioral hardware description language code. This is enabled by introducing a metric for the on-line testability. A new variation of duplication (namely inversion testing) is also proposed and used, providing the system with an additional degree of freedom for minimizing hardware overheads associated with test resource insertion. Considering the on-line testability within the synthesis process facilitates fast and painless design space exploration, resulting in a versatile high-level-synthesis process, capable of producing alternative realizations according to the designers directions, for alternative target technologies. Finally, the fault escape probability of the overall scheme is discussed theoretically and evaluated experimentally

Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric

There have been several recent attempts to include duplication-based on-line testability in behaviourally synthesized designs. In this paper, on-line testability is considered within the optimisation process of iterative, cost function-driven high-level synthesis, such that on-line testing resources are inserted automatically without any modification of the source HDL code. This involves the introduction of a metric for on-line testability. A variation of duplication testing (namely inversion testing) is also used, providing the system with an additional degree of freedom towards minimising hardware overheads associated with test resource insertion. Considering on-line testability within the synthesis process facilitates fast and efficient design space exploration, resulting in a versatile high-level synthesis process, capable of producing alternative realisations according to the designers directions.

Implementing cryptography on TFT technology for secure display applications

Several recent studies have underlined the need for trusted information displays in current and future personal devices. On the other hand, the display market is more and more dominated by low-cost flat-panel structures, driven by Thin-Film Transistor (TFT) circuits. Further, the quality of TFT-based electronics is constantly improving, allowing the fabrication of complicated electronic circuits on TFT technology. We have embarked on a project to implement cryptographic algorithms on polysilicon TFT technology. Our prototype designs will pave the way for secure display realisations combining cryptographic circuits and conventional pixel drivers on the same substrate. An experimental Data Encryption Standard (DES) coprocessor on polysilicon TFT technology is under development, while we are investigating a vector processor architecture to implement Elliptic Curve Cryptography (ECC).

Foundation of combined datapath and controller self-checking design

We consider the problem of designing self-checking controllers for applications with sequential datapaths. Firstly we compare encoded and unencoded (one-hot) controller implementations and we argue that self-checking of encoded control signals is not sufficient in terms of testability. Subsequently, we present four alternative controller self-checking schemes, based both on parity and on the observation that a self-checking data path can be employed for control path self-checking as well, by exploiting intrinsically secure control states. We discuss the properties of each of them, and present a few experimental results.

An Asynchronous PLA with Improved Security Characteristics

Programmable logic arrays (PLAs) present an alternative to logic-gate based design. We propose the transistor level structure of a PLA for single-rail asynchronous applications. The geometrically regular layout together with the deployment of dynamic logic help us fine-tune the PLA to enhance its resistance to side-channel attacks, while parity prediction and checking is employed to protect against malicious fault injection. Finally, we demonstrate how our PLAs can be used as building blocks of large-scale systems with good security characteristics, when combined with special return-to-zero asynchronous latches

Transformation based insertion of on-line testing resources in a high-level synthesis environment

On-line testability is essential in designs with high reliability requirements. High-level synthesis reduces time-to-market and enables efficient design space exploration. In our work, we implement on-line testable designs in a high-level synthesis context. We refer to our new technique (inversion testing) and exploit its features, in an attempt to reduce hardware penalties.