Phichet Moungnoul

OTA-based high frequency CMOS multiplier and squaring circuit

A gigahertz analog multiplier based on OTA and squaring is proposed. The multiplier has gigahertz frequency response is suitable to use in communication system. The circuit is based on 0.18 μm CMOS technology simulated using PSPICE level 7. This technique provides; wide dynamic range, GHz-bandwidth response and low power consumption. The proposed circuit has been simulated with PSPICE and achieved −3dB bandwidth of 3.96GHz. The total power dissipation is 0.588mW with ±1V power supply voltages..

GSM Traffic Forecast by Combining Forecasting Technique

This paper proposes a traffic forecasting by combining two forecasting techniques, which are the least square method and linear regression method, to perform the better forecasting, close to the existing real world. The result of this forecasting will be used in optimization of the GSM mobile telephone system. From the result, it shows that the combining forecasting gives the close result to the existing real world than using only one of two forecasting techniques

Current-mode universal filter using translinear current conveyors

This paper presents a new current-mode universal filter with three inputs and three outputs employing only two multiple-output current-controlled current conveyors and two grounded capacitors. The proposed circuit can simultaneously realize of lowpass, bandpass, highpass and bandstop current responses from same configuration. The proposed filter also enjoys an independent current control of parameters natural angular frequency and quality factor through adjusting the bias currents of the translinear current conveyors. The proposed configuration no requires of any cancellation constrain for realizing all the filter responses. The characteristics of the proposed circuit are simulated using PSPICE to confirm the theory.

A GHz Simple CMOS Squarer Circuit

A simple CMOS squarer circuit is proposed. The circuit has a Giga Hertz frequency response that has advantages to be used in communication systems. The proposed circuit focuses on the extension to ultra wide bandwidth. The circuit is based on 0.18 mum CMOS technology simulated using PSPICE level 7. The circuit has wide dynamic range, GHz-bandwidth response and low power consumption. The proposed circuit has been simulated with SPICE and achieved -3 dB bandwidth of 10.96 GHz. The power consumption is about 86.51muW with a plusmn 1 V power supply voltage. Simulation result shows that the proposed squarer can accommodate the whole UWB bandwidth.

A GHz analog multiplier for UWB communications

A gigahertz wideband analog multiplier is proposed. The multiplier based on the MOS cascade operation circuit. The inputs are in voltage mode and become in current mode after multiplication. The result shows that the multiplier can be applied for UWB communications. The circuit is based on 0.18 mum CMOS technology simulated using HSPICE with level 49.

An FPGA Architecture for ASIC-FPGA Co-design to Streamline Processing of IDSs

Novel methods for unauthorized access are always made. For cyber security measures in mobile devices, low-power and high-speed processing is very important. Despite these situations, a CPU for mobile devices is a very low processing capacity in order to focus on low-power operations and does not have sufficient performance for processing detection processing for unauthorized access. In contrast, a field-programmable gate array (FPGA) can apply to cyber security processing on mobile devices. By using the FPGA, cyber security processing is able to use parallel processing, super pipeline and processing that is independent of a word width size. However, the FPGA has a problem that the delay times of arithmetic circuits are longer than that of an application specific integrated circuit (ASIC) or CPU. In this paper, the authors propose an FPGA architecture for ASIC-FPGA co-design for addressing the problem. In order to evaluate the architecture, adders are enhanced by ASIC-FPGA co-design and evaluated. As a result, it is shown that the problem with the delay times of arithmetic circuits is solved.

Wiring control by RTL design for reconfigurable wave-pipelined circuits

High-speed and low-power circuits of considering the development cycle for digital signal processing are very important in a mobile computing. The achievement of them on an FPGA (Field Programmable Gate Array) dominant in the point of shortening the development cycle. Nevertheless a reconfigurable device such as an FPGA for a power-aware design has not been developed. The authors have developed logic blocks for reconfigurable wave-pipelined circuits for the achievement of high-speed and low-power reconfigurable circuits. Wave-pipeline is one of a circuit design technique for high-speed processing and low-power consumption. They are very useful for the reduction in the resource on the FPGA. However, a wiring control to connect them have not been achieved. In this paper, the wiring control by RTL Design is developed. Its operation speeds are evaluated using 0.18 um CMOS technology.

A 0.18 μm CMOS Gaussian Monocycle Pulse Circuit Design for UWB

This paper proposes a new method of monocycle pulse generation by generating the Gaussian pulse, and generate first derivative of the pulse to get a Scholtzs monocycle pulse. The simulation result of the generation is based on 0.18 μm CMOS technology which achieved using HSPICE (Level 49). The Gaussian pulse is generated by using CMOS inverter of which is applied the delay time to perform the Gaussian pulse

The Potential of Routers Configured with the Switch Matrix by RTL

In this paper, analysis results of an FPGA (Field-Programmable Gate Array) designed in RTL (Register Transfer Level) shows that does not have a problem in routing. It has many advantages than conventional FPGA developed by the transistor level. However, the crossbar switch of the FPGA designed in RTL has a problem with the direction of the signal. The direction is fixed in one direction unlike the conventional crossbar switch. Routing is analyzed by using the circuit of three input two output.

Compatible WEP algorithm for improved cipher strength and high-speed processing

As a cipher algorithm of Wi-Fi (Wireless Fidelity) networks based on IEEE 802.11b/g/h standards, WEP (Wired Equivalent Privacy) is widely used and can correspond to most Wi-Fi devices. However, the method of deciphering WEP has already been clarified and it is executed in several seconds. Nevertheless, a lot of Wi-Fi APs (Access Points) use it because a part of equipment has only WEP in the cipher function. Additionally, some mobile processors demand algorithm a cipher of low load. In this paper, the authors propose a compatible WEP algorithm to which cipher strength is strengthened. The algorithm is implemented with software and evaluated. As a result, it is shown that processing speed of the compatible WEP algorithm is more high-speed than that of the conventional WEP algorithm.