Philippe Gendrier

Voltage Glitch Attacks on Mixed-Signal Systems

Supply voltage glitches are a well-known fault injection method used to attack electronic circuits. The aim of this paper is to identify the specific threats of mixed signal systems and to provide some solutions to ensure their security. Indeed, many Systems on Chip use both analog and digital circuits but, most of the time, the security of such application is considered only from an exclusively digital or sometimes analog point of view. However, in mixed-signals systems, analog and digital solutions coexist and must be considered as a unique system to ensure the security of the whole application. In this purpose, this paper gives an overview of voltage glitch attacks effects and countermeasures for analog and digital blocks as part of Mixed-Signal SoCs (AMS-SoCs). It also emphasizes the unique behavior of mixed-signal circuits during glitch attacks and suggest some guidelines to associate efficiently analog and digital solutions to secure a mixed-signal system.

Power supply glitch attacks: Design and evaluation of detection circuits

Techniques using modification of power supplies to attack circuits do not require strong expertise or expensive equipment. Supply voltage glitches are then a serious threat to the security of electronic devices. In this paper, mechanisms involved during such attacks are analyzed and described. It is shown that timing properties of logic gates are very sensitive to power glitches and can be used to inject faults. For this reason, detection circuits which monitor timing properties of dedicated paths are designed to detect glitch attacks. To validate these solutions, a new approach based on the study of propagation delay variation is also presented. Following this approach, the performance of detection circuits can be evaluated at design level using a standard digital design flow.

Detecting positive voltage attacks on CMOS circuits

This work investigates voltage attacks over the nominal voltage on CMOS digital circuits designed on advanced technology nodes. The behavior of both combinatorial and sequential logic is analyzed in presence of static and dynamic overvoltage attacks. It points out that only modifications of propagation delays occur in presence of such attacks. Timing detection circuits are then introduced to detect hold violations. These circuits offer good performance with low area overhead but their implementation require extra timing constraints on the design to protect. In addition, multiple power domain circuits must be considered to thwart overpowering attacks.

Power analysis methodology for secure circuits

A study on power consumption of a digital synchronous circuit in advanced CMOS technology is performed. These technologies target low power applications allowing accurate power analysis. A model of power signature is developed to identify data related consumption using current consumption and power delivery network capacitance at design phase. In addition to digital power characterization tool, device junction capacitance is extracted and used to provide an accurate power signature. Simulations are compared to experimental traces on a synchronous digital circuit to validate the approach. This model can also be used for complex analog/digital circuit. Finally two countermeasures masking and decoupling capacitance flattening are analyzed with our methodology in early design phase allowing to anticipate silicon tests.

A novel memory array based on an annular single-poly EPROM cell for use in standard CMOS technology

Within the scope of non-volatile memories, CMOS compatibility and portability are serious issues. We describe here an edgeless single-poly floating gate p-channel memory cell, which can be embedded into a novel memory array architecture. It features high electrical performance together with a robustness with respect to the process. It has been processed in a 0.18 /spl mu/m HCMOS technology from STMicroelectronics, Crolles.