Philippe Roussel

Variability aware modeling for yield enhancement of SRAM and logic

Anticipating silicon response in the presence or process variability is essential to avoid costly silicon re-spins. EDA industry is trying to provide the right set of tools to designers for statistical characterization of SRAM and logic. Yet design teams (also in foundries) are still using classical corner based characterization approaches. On the one hand the EDA industry fails to meet the demands on the appropriate functionality of the tools. On the other hand, design teams are not yet fully aware of the trade-offs involved when designing under extreme process variability. This paper summarizes the challenges for statistical characterization of SRAM and logic. It describes the key features of a set of prototype tools addressing that required functionality together with their application to a number of case studies aiming at enhancing yield at product level.

Exponent monte carlo for quick statistical circuit simulation

The main goals of this article are to report an implementation and a quantitative study of Exponent Monte Carlo, an enhanced version of Monte Carlo for verifying high circuit yield in the presence of random process variations. Results on industry-grade standard cell netlists and compact models in 45nm show that EMC predicts reasonable results at least 1,000 times faster than MC.

Experimental validation of self-heating simulations and projections for transistors in deeply scaled nodes

CMOS device improvements have recently been achieved by changing the geometry of the device from planar to fully-depleted (FD) FinFET. Also FD SOI (Silicon-on-Isolator) devices have emerged as a candidate for replacing bulk silicon in ULSI applications in future technology nodes. Along with this scaling comes, however, a challenging penalty: device self-heating. In this study, i) we propose a unique measurement technique for self-heating and use it to assess self-heating in planar devices, ii) we compare and verify these results with finite-element simulations and iii) we provide perspectives for upcoming FinFET nodes.

Characterization and simulation methodology for time-dependent variability in advanced technologies

This paper describes the implications of Bias Temperature Instability (BTI) related time-dependent threshold voltage distributions on the performance and yield of devices and SRAM cells. We show that nFET and pFET time-dependent variability, in addition to the standard time-zero variability, can be fully characterized and projected using a series of measurements on a large test element group (TEG) fabricated in an advanced technology. The statistical distributions encompassing both time-zero and time-dependent variability and their correlations are discussed. The assumption of Normally distributed threshold voltages, imposed by State-of-the-Art design approaches, is shown to induce inaccuracy which is readily solved by adopting our defect-centric statistical approach.

Reliability in gate first and gate last ultra-thin-EOT gate stacks assessed with CV-eMSM BTI characterization

CMOS device improvements have recently been achieved by aggressive scaling of effective oxide thickness (EOT) in Gate First (GF) integration schemes using interfacial layer scavenging. Along with this scaling comes, however, a challenging reliability penalty. Therefore, to decrease the turnaround time of experimental gate stacks, we demonstrate a technique to quantitatively evaluate the long-term bias temperature instability (BTI) behavior of gate stacks on capacitors instead of transistors. We prove that this technique yields comparable results as standard extended measure-stress-measure (eMSM) IV-BTI measurements. Subsequently, we demonstrate in such a short turnaround time experiment that we can achieve scavenging in a Gate Last (GL) processing scheme. Finally, by benefitting from our proposed technique, we conclude that our Gate Last stacks are still more susceptible to BTI than our Gate First stacks with similar EOT.

Impact of process variability on the radiation-induced soft error of nanometer-scale srams in hold and read conditions

Process variation affects the soft-error sensitivity of SRAM cells. A complex dependence on the arrival time of the particle strike relative to the word-line clock is observed.

Four point probe ramped voltage stress as an efficient method to understand breakdown of STT-MRAM MgO tunnel junctions

The study of reliability and understanding of the MgO barrier breakdown mechanism is essential for the development of STT-MRAM, a promising non-volatile memory. However, for STT-MRAM it is unclear what the preferred method is for studying barrier breakdown. In this paper we compare four point probe Ramped Voltage Stress (4PP-RVS) with a conventional Constant Voltage Stress (CVS) technique and with pulsed breakdown (RF-BD). We show the equivalence of breakdown time distributions determined by 4PP-RVS and CVS. 4PP makes the investigation of area scaling possible and avoids potential lifetime misjudgments of more than one order of magnitude. In a short and predictable time RVS can measure large populations subject to strong lifetime variability, typical for STT-MRAM cells. We also compare 4PP-RVS with pulsed breakdown (RF-BD) and observe a more favorable reliability for RF-BD. 4PP-RVS allows an efficient in depth breakdown analysis for STT-MRAM.

Voltage acceleration and pulse dependence of barrier breakdown in MgO based magnetic tunnel junctions

STT-MRAM is a promising non-volatile memory. For reliable lifetime predictions, a correct voltage acceleration model is essential. However, there is no consensus over what acceleration model to use. In this paper we study barrier breakdown time over an extended time range. With a maximum likelihood ratio method, we test the statistical significance of fits for different voltage acceleration models. We find that the power law best describes voltage acceleration. In addition we observe that the breakdown time is independent of duty cycle or pulse width.

Defect-centric perspective of combined BTI and RTN time-dependent variability

This paper describes the implications of time-dependent threshold voltage variability, induced by Bias Temperature Instability (BTI) and Random Telegraph Noise (RTN), on the reliability and performance of advanced technology nodes. Investigation of time-dependent variability at the individual trap level, e.g. in production environments, is not feasible with approaches such as single device measurements developed in the academic literature. Nonetheless, nFET and pFET time-dependent variability, in addition to standard time-zero variability, can be fully characterized and projected using a series of measurements on a large test element group. The statistical distributions encompassing both BTI and RTN variability and their correlations are discussed from a defect-centric perspective.

Statistical characterization of standard cells using design of experiments with response surface modeling

This paper presents an approach for statistical characterization of standard cells based on a combination of Statistical Design of Experiments (S-DoE) and Response Surface Modeling. Unlike both, most of the State-of-the-Art and Sensitivity Analysis (SA) techniques currently offered by EDA vendors, S-DoE preserves the underlying correlation among process variation parameters. This results in about two orders of magnitude of statistical accuracy improvement, yet it features an electrical simulation effort linear to the cell complexity. The technique is validated using a representative subset of standard cells using a 32nm statistical Physical Design Kit.