Dimitri Linten

The Potential of FinFETs for Analog and RF Circuit Applications

CMOS downscaling in the nanoscale era will necessitate drastic changes to the planar bulk CMOS transistor to keep pace with the required speed increase while at the same time maintaining acceptable performance in terms of leakage, variability and analog parameters such as gain, noise and linearity. For the gate electrode and the gate dielectric, which classically use polysilicon and with some amount of nitridation, new materials might be needed. Also, a new transistor architecture might be required that deviates from the planar structure. Thanks to their inherent suppression of short-channel effects, reduced drain-induced barrier lowering and good scalability, multi-gate devices such as fin-shaped field-effect transistors (FinFETs) are considered as possible candidates for device scaling at the end of International Technology Roadmap for Semiconductors. As such, they form a first step between a planar architecture and a silicon nanowire. In this paper, we demonstrate with functional prototypes of analog and RF circuits that the combination of a new gate stack with a FinFET transistor architecture outperforms comparable circuit realizations in planar bulk CMOS for low to moderate speed. Further, the FinFETs exhibit less leakage and show less intra-die variability than their planar bulk counterpart. In the microwave and millimeter-wave frequency region, planar bulk CMOS is still superior. The main challenge for FinFET performance in the coming years is the improvement of the maximum cutoff frequency, which is nowadays limited to 100 GHz.

Neutron-Induced Failure in Silicon IGBTs, Silicon Super-Junction and SiC MOSFETs

50 MeV and 80 MeV neutron-induced failure is investigated for several types of power devices (super-junction, IGBT and SiC) from different vendors. A strong dependence on the device type and orientation is observed.

Investigating ESD sensitivity in electrostatic SiGe MEMS

The sensitivity of electrostatically actuated SiGe microelectromechanical systems to electrostatic discharge events has been investigated in this paper. Torsional micromirrors and RF microelectromechanical systems (MEMS) actuators have been used as two case studies to perform this study. On-wafer electrostatic discharge (ESD) measurement methods, such as the human body model (HBM) and machine model (MM), are discussed. The impact of HBM ESD zap tests on the functionality and behavior of MEMS is explained and the ESD failure levels of MEMS have been verified by failure analysis. It is demonstrated that electrostatic MEMS devices have a high sensitivity to ESD and that it is essential to protect them.

Characterization and simulation methodology for time-dependent variability in advanced technologies

This paper describes the implications of Bias Temperature Instability (BTI) related time-dependent threshold voltage distributions on the performance and yield of devices and SRAM cells. We show that nFET and pFET time-dependent variability, in addition to the standard time-zero variability, can be fully characterized and projected using a series of measurements on a large test element group (TEG) fabricated in an advanced technology. The statistical distributions encompassing both time-zero and time-dependent variability and their correlations are discussed. The assumption of Normally distributed threshold voltages, imposed by State-of-the-Art design approaches, is shown to induce inaccuracy which is readily solved by adopting our defect-centric statistical approach.

Neutron-induced failure in super-junction, IGBT, and SiC power devices

50 MeV and 80 MeV neutron-induced failure is investigated for several types of power devices (super-junction, IGBT and SiC) from different vendors. A strong dependence on the device type and orientation is observed.

Mechanical response of electrostatic actuators under ESD stress

In this work, the mechanical response of electrostatic MEMS actuators during ESD stress has been measured and reported for the first time. The failure mechanism of the actuators during ESD has been studied and compared with failure under low frequency (∼DC) voltage overstress. Electrical and mechanical failure modes have been distinguished and correlated to enable better understanding of the failure physics. Measuring the mechanical response during ESD stress tests has been demonstrated to be very important to characterize the reliability of electrostatic MEMS actuators. An experimental set-up for the same has been demonstrated and compared with a conventional ESD tester.

Impact of process variability on the radiation-induced soft error of nanometer-scale srams in hold and read conditions

Process variation affects the soft-error sensitivity of SRAM cells. A complex dependence on the arrival time of the particle strike relative to the word-line clock is observed.

Relaxation of time-dependent NBTI variability and separation from RTN

NBTI and RTN time-dependent variability is described from a defect-centric perspective. It is shown that NBTI induced threshold voltage shift (ΔVTH) distribution is governed by a compound Exponential-Poisson process. Using the memoryless properties of Poisson statistics, it is shown that not only the stressed but also the relaxed fraction follows the Exponential-Poisson distribution. Moreover, the relaxed fraction is shown to be independent from the final remaining ΔVTH. Using the same statistical model, the separation of RTN induced ΔVTH from NBTI is shown which allows a more accurate estimation of the characteristic distribution parameters. Finally, it is shown that RTN is a wide-sense stationary noise source of which the autocorrelation can be extracted from analysis of NBTI relaxation traces.

Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies

CMOS scaling beyond 45nm requires devices that deviate from the planar bulk transistor with a polysilicon gate and nitrided silicon dioxide (SiON) as gate dielectric. To downscale planar bulk devices, strain is used to boost mobility and new materials are introduced in the gate stack. Multigate devices such as fully-depleted SOI FinFETs (Fig. 29.4.1) are also candidates for downscaling beyond 45nm.

Defect-centric perspective of combined BTI and RTN time-dependent variability

This paper describes the implications of time-dependent threshold voltage variability, induced by Bias Temperature Instability (BTI) and Random Telegraph Noise (RTN), on the reliability and performance of advanced technology nodes. Investigation of time-dependent variability at the individual trap level, e.g. in production environments, is not feasible with approaches such as single device measurements developed in the academic literature. Nonetheless, nFET and pFET time-dependent variability, in addition to standard time-zero variability, can be fully characterized and projected using a series of measurements on a large test element group. The statistical distributions encompassing both BTI and RTN variability and their correlations are discussed from a defect-centric perspective.