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Publication
Featured researches published by Phillip J. Oldiges.
international conference on simulation of semiconductor processes and devices | 2015
Jiseok Kim; Phillip J. Oldiges; Hui-feng Li; Hiroaki Niimi; Mark Raymond; Peter Zeitzoff; Vimal Kamineni; Praneet Adusumilli; Chengyu Niu; F. Chafik
We have theoretically investigated the specific contact resistivity of n-type Si and Ge metal-insulator-semiconductor contacts with various insulating oxides. We have found a significant reduction of the contact resistivity for both Si and Ge with an insertion of insulators at low and moderate donor doping levels. However, at the higher doping levels (>1020 cmu-3), the reduction of the contact resistivity is negligible and the contact resistivity increases as the insulator thickness increase. Thus, we have shown that the lowest possible contact resistivity can be achieved with the metal-semiconductor contact with highest possible activated doping density.
international conference on simulation of semiconductor processes and devices | 2002
Meikei Ieong; Phillip J. Oldiges
New physical models, algorithms, and parameters are needed to accurately model emerging silicon-on-insulator (SOI) devices. We discuss key modeling tools and methodologies used to support research, development, and manufacturing of emerging SOI device technology. Although commercial TCAD tools are available, new physical models, parameters, and algorithms are needed to study these novel device structures.
international conference on simulation of semiconductor processes and devices | 2011
Phillip J. Oldiges; R. Muralidhar; Pranita Kulkarni; C-H. Lin; K. Xiu; D. Guo; M. Bajaj; N. Sathaye
Modeling challenges and solutions for silicon based high performance device options at the 14nm node are presented. A variety of devices are being considered, using a variety of methods to analyze the devices objectively. Partially depleted silicon on insulator (PDSOI) devices are compared against extremely thin (ETSOI) and FinFET devices.
international conference on simulation of semiconductor processes and devices | 2011
Pranita Kulkarni; Qing Liu; Ali Khakifirooz; Ying Zhang; Kangguo Cheng; F. Monsieur; Phillip J. Oldiges
We present a detailed analysis of substrate bias (Vbb) impact on gate induced drain leakage (GIDL) for thin-BOX extremely thin silicon-on-insulator (ETSOI) with BOX thickness (TBOX) ranging from 10 to 50 nm and inversion layer thicknesses (TINV) ranging from 1.1 to 1.3 nm. The GIDL behavior for thin-BOX under various substrate biases (Vbb) and partially depleted SOI (PDSOI) devices with different body doping are compared.
international conference on simulation of semiconductor processes and devices | 2002
Phillip J. Oldiges; C. Murthy; Xinlin Wang; S. Fung; R. Purtell
A detailed simulation and analysis of the source/drain resistance is performed. It is shown that the placement and depth of silicide regions can have a strong influence on the total source/drain resistance. Simulations further show that moving the silicided regions closer to the channel of a device will not necessarily decrease source/drain resistance, and may actually cause the resistance to increase. Lumped contact resistance, distributed resistance, Schottky contact models, and a new local distributed resistance model are compared.
international conference on simulation of semiconductor processes and devices | 2000
Phillip J. Oldiges; Qimghuamg Lin; K. Petrillo; M. Sanchez; Meikei Ieong; M. Hargrove
Archive | 2006
Huilong Zhu; Bruce B. Doris; Meikei Ieong; Phillip J. Oldiges; Min Yang
Archive | 2013
Jeffrey B. Johnson; Phillip J. Oldiges; Viorel Ontalus; Kai Xiu
Archive | 2014
Jeffrey B. Johnson; Phillip J. Oldiges; Viorel Ontalus; Kai Xiu
Archive | 2012
Jeffrey B. Johnson; Phillip J. Oldiges; Viorel Ontalus; Kai Xiu